Details of a Researcher - Matsutani, Hiroki

Papers - Matsutani, Hiroki

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A traffic-aware memory-cube network using bypassing

Shikama Y., Kawano R., Matsutani H., Amano H., Nagasaka Y., Fukumoto N., Koibuchi M.

Microprocessors and Microsystems (Microprocessors and Microsystems) 90 2022.04

ISSN 01419331

Three-dimensional stack memory which provides both high-bandwidth access and large capacity is a promising technology for next-generation computer systems. While a large number of memory cubes increase the aggregate memory capacity, the communication latency and power consumption increase significantly owing to its low-radix large-diameter packet network. In this context, we propose a memory-cube network called Diagonal Memory Network (DMN). A diagonal network topology, its floor layout, and its lightweight router were designed for low-latency and low-voltage memory-read communication. DMN routing efficiently avoids deadlocks of packets, although it allows each packet transmitted to a processor to use both bypassing and original datapaths. Our evaluation results show that the DMN router decreases the use of hardware resources by more than 31% compared with a conventional virtual channel router. The DMN router reduces energy consumption by 13% and 67% to transit a packet along with the original datapath and bypassing datapath, respectively. Furthermore, using flit-level discrete event simulation, a DMN topology achieves high throughput and latency that is lower than that of existing network topologies using conventional packet routers.

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An Overflow/Underflow-Free Fixed-Point Bit-Width Optimization Method for OS-ELM Digital Circuit

Tsukada M., Matsutani H.

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences) 105 ( 3 ) 437 - 447 2022

ISSN 09168508

Currently there has been increasing demand for real-time training on resource-limited IoT devices such as smart sensors, which realizes standalone online adaptation for streaming data without data transfers to remote servers. OS-ELM (Online Sequential Extreme Learning Machine) has been one of promising neural-network-based online algorithms for on-chip learning because it can perform online training at low computational cost and is easy to implement as a digital circuit. Existing OS-ELM digital circuits employ fixed-point data format and the bit-widths are often manually tuned, however, this may cause overflow or underflow which can lead to unexpected behavior of the circuit. For on-chip learning systems, an overflow/underflow-free design has a great impact since online training is continuously performed and the intervals of intermediate variables will dynamically change as time goes by. In this paper, we propose an overflow/underflow-free bit-width optimization method for fixed-point digital circuits of OS-ELM. Experimental results show that our method realizes overflow/underflow-free OS-ELM digital circuits with 1.0x - 1.5x more area cost compared to the baseline simulation method where overflow or underflow can happen.

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GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph

Kawano R., Matsutani H., Koibuchi M., Amano H.

ACM International Conference Proceeding Series (ACM International Conference Proceeding Series) 51 - 55 2021.06

The design of the network topology of a large-scale parallel computer system can be represented as an order/degree problem in the graph theory. To solve the order/degree problem, we have to obtain all-pairs-shortest-path (APSP) for the graph. A conventional APSP algorithm for GPUs is based on the adjacency matrix (ADJ-APSP). When focusing on low-degree and unweighted graphs, most of the matrix elements are zero in the first few iterations of the algorithm. We will further speed up the APSP algorithm by treating the adjacency matrix as a sparse matrix in the first iterations of the algorithm. Evaluation results show that our proposed algorithm on a single GPU (NVIDIA GeForce RTX 3080) reduces the execution time by up to 32.7 % compared to the conventional algorithm.

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An area-efficient recurrent neural network core for unsupervised time-series anomaly detection

SAKUMA T., MATSUTANI H.

IEICE Transactions on Electronics (IEICE Transactions on Electronics) 1 ( 6 ) 247 - 256 2021.06

ISSN 09168524

Since most sensor data depend on each other, time-series anomaly detection is one of practical applications of IoT devices. Such tasks are handled by Recurrent Neural Networks (RNNs) with a feedback structure, such as Long Short Term Memory. However, their learning phase based on Stochastic Gradient Descent (SGD) is computationally expensive for such edge devices. This issue is addressed by executing their learning on high-performance server machines, but it introduces a communication overhead and additional power consumption. On the other hand, Recursive Least-Squares Echo State Network (RLS-ESN) is a simple RNN that can be trained at low cost using the least-squares method rather than SGD. In this paper, we propose its area-efficient hardware implementation for edge devices and adapt it to human activity anomaly detection as an example of interdependent time-series sensor data. The model is implemented in Verilog HDL, synthesized with a 45 nm process technology, and evaluated in terms of the anomaly capability, hardware amount, and performance. The evaluation results demonstrate that the RLS-ESN core with a feedback structure is more robust to hyper parameters than an existing Online Sequential Extreme Learning Machine (OS-ELM) core. It consumes only 1.25 times larger hardware amount and 1.11 times longer latency than the existing OS-ELM core.

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Accelerating ODE-Based Neural Networks on Low-Cost FPGAs

Watanabe H., Matsutani H.

2021 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2021 - In conjunction with IEEE IPDPS 2021 (2021 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2021 - In conjunction with IEEE IPDPS 2021) 88 - 95 2021.06

ISSN 9781665435772

ODENet is a deep neural network architecture in which a stacking structure of ResNet is implemented with an ordinary differential equation (ODE) solver. It can reduce the number of parameters and strike a balance between accuracy and performance by selecting a proper solver. It is also possible to improve the accuracy while keeping the same number of parameters on resource-limited edge devices. In this paper, using Euler method as an ODE solver, a part of ODENet is implemented as a dedicated logic on a low-cost FPGA (Field-Programmable Gate Array) board, such as PYNQ-Z2 board. As ODENet variants, reduced ODENets (rODENets) each of which heavily uses a part of ODENet layers and reduces/eliminates some layers differently are proposed and analyzed for low-cost FPGA implementation. They are evaluated in terms of parameter size, accuracy, execution time, and resource utilization on the FPGA. The results show that an overall execution time of an rODENet variant is improved by up to 2.66 times compared to a pure software execution while keeping a comparable accuracy to the original ODENet.

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An FPGA-Based On-Device Reinforcement Learning Approach using Online Sequential Learning

Watanabe H., Tsukada M., Matsutani H.

ISSN 9781665435772

DQN (Deep Q-Network) is a method to perform Q-learning for reinforcement learning using deep neural networks. DQNS require a large buffer and batch processing for an experience replay and rely on a backpropagation based iterative optimization, making them difficult to be implemented on resource-limited edge devices. In this paper, we propose a lightweight on-device reinforcement learning approach for low-cost FPGA devices. It exploits a recently proposed neural-network based on-device learning approach that does not rely on the backpropagation method but uses OS-ELM (Online Sequential Extreme Learning Machine) based training algorithm. In addition, we propose a combination of L2 regularization and spectral normalization for the on-device reinforcement learning so that output values of the neural network can be fit into a certain range and the reinforcement learning becomes stable. The proposed reinforcement learning approach is designed for PYNQ-Z1 board as a low-cost FPGA platform. The evaluation results using OpenAI Gym demonstrate that the proposed algorithm and its FPGA implementation complete a CartPole-v0 task 29.77x and 89.40x faster than a conventional DQN-based approach when the number of hidden-layer nodes is 64.

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Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths

Shikama Y., Kawano R., Matsutani H., Amano H., Nagasaka Y., Fukumoto N., Koibuchi M.

Proceedings - 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2021 (Proceedings - 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2021) 143 - 147 2021.03

ISSN 9781665414555

Three-dimensional stack memory that provides both high-bandwidth access and large capacity is a promising technology for next-generation computer systems. While a large number of memory cubes increase the aggregate memory capacity, the communication latency and power consumption would become significant due to its low-radix large-diameter packet network. In this context, we propose a memory-cube network called Diagonal Memory Network (DMN). A diagonal network topology, its floor layout, and its lightweight router are designed for low-latency and low-voltage memory-read communication. Our evaluation results show that a DMN router decreases 31% of the hardware resources than a conventional virtual-channel router. The DMN router reduces 13% and 67% energy consumption to transit a packet along with the original datapath and bypassing datapath, respectively.

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An FPGA-based optimizer design for distributed deep learning with multiple GPUs

Itsubo T., Koibuchi M., Amano H., Matsutani H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E104D ( 12 ) 2057 - 2067 2021

ISSN 09168532

Since deep learning workloads perform a large number of matrix operations on training data, GPUs (Graphics Processing Units) are efficient especially for the training phase. A cluster of computers each of which equips multiple GPUs can significantly accelerate the deep learning workloads. More specifically, a back-propagation algorithm following a gradient descent approach is used for the training. Although the gradient computation is still a major bottleneck of the training, gradient aggregation and optimization impose both communication and computation overheads, which should also be reduced for further shortening the training time. To address this issue, in this paper, multiple GPUs are interconnected with a PCI Express (PCIe) over 10Gbit Ethernet (10GbE) technology. Since these remote GPUs are interconnected with network switches, gradient aggregation and optimizers (e.g., SGD, AdaGrad, Adam, and SMORMS3) are offloaded to FPGA-based 10GbE switches between remote GPUs; thus, the gradient aggregation and parameter optimization are completed in the network. The proposed FPGA-based 10GbE switches with the four optimizers are implemented on NetFPGA-SUME board. Their resource utilizations are increased by PEs for the optimizers, and they consume up to 56% of the resources. Evaluation results using four remote GPUs connected via the proposed FPGA-based switch demonstrate that these optimizers are accelerated by up to 3.0x and 1.25x compared to CPU and GPU implementations, respectively. Also, the gradient aggregation throughput by the FPGA-based switch achieves up to 98.3% of the 10GbE line rate.

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An On-Device Federated Learning Approach for Cooperative Model Update between Edge Devices

Ito R., Tsukada M., Matsutani H.

IEEE Access (IEEE Access) 9 92986 - 92998 2021

Most edge AI focuses on prediction tasks on resource-limited edge devices while the training is done at server machines. However, retraining or customizing a model is required at edge devices as the model is becoming outdated due to environmental changes over time. To follow such a concept drift, a neural-network based on-device learning approach is recently proposed, so that edge devices train incoming data at runtime to update their model. In this case, since a training is done at distributed edge devices, the issue is that only a limited amount of training data can be used for each edge device. To address this issue, one approach is a cooperative learning or federated learning, where edge devices exchange their trained results and update their model by using those collected from the other devices. In this paper, as an on-device learning algorithm, we focus on OS-ELM (Online Sequential Extreme Learning Machine) to sequentially train a model based on recent samples and combine it with autoencoder for anomaly detection. We extend it for an on-device federated learning so that edge devices can exchange their trained results and update their model by using those collected from the other edge devices. This cooperative model update is one-shot while it can be repeatedly applied to synchronize their model. Our approach is evaluated with anomaly detection tasks generated from a driving dataset of cars, a human activity dataset, and MNIST dataset. The results demonstrate that the proposed on-device federated learning can produce a merged model by integrating trained results from multiple edge devices as accurately as traditional backpropagation based neural networks and a traditional federated learning approach with lower computation or communication cost.

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An FPGA Acceleration and Optimization Techniques for 2D LiDAR SLAM Algorithm<sup>∗</sup>

Sugiura K., Matsutani H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E104D ( 6 ) 789 - 800 2021

ISSN 09168532

An efficient hardware implementation for Simultaneous Localization and Mapping (SLAM) methods is of necessity for mobile autonomous robots with limited computational resources. In this paper, we propose a resource-efficient FPGA implementation for accelerating scan matching computations, which typically cause a major bottleneck in 2D LiDAR SLAM methods. Scan matching is a process of correcting a robot pose by aligning the latest LiDAR measurements with an occupancy grid map, which encodes the information about the surrounding environment. We exploit an inherent parallelism in the Rao-Blackwellized Particle Filter (RBPF) based algorithm to perform scan matching computations for multiple particles in parallel. In the proposed design, several techniques are employed to reduce the resource utilization and to achieve the maximum throughput. Experimental results using the benchmark datasets show that the scan matching is accelerated by 5.31-8.75× and the overall throughput is improved by 3.72-5.10× without seriously degrading the quality of the final outputs. Furthermore, our proposed IP core requires only 44% of the total resources available in the TUL Pynq-Z2 FPGA board, thus facilitating the realization of SLAM applications on indoor mobile robots.

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An Edge Attribute-Wise Partitioning and Distributed Processing of R-GCN Using GPUs

Kibata T., Tsukada M., Matsutani H.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)) 12480 LNCS 122 - 134 2021

ISSN 9783030715922

R-GCN (Relational Graph Convolutional Network) is one of GNNs (Graph Neural Networks). The model tries predicting latent information by considering directions and types of edges in graph-structured data, such as knowledge bases. The model builds weight matrices to each edge attribute. Thus, the size of the neural network increases linearly with the number of edge types. Although GPUs can be used for accelerating the R-GCN processing, there is a possibility that the size of weight matrices exceeds GPU device memory. To address this issue, in this paper, an edge attribute-wise partitioning is proposed for R-GCN. The proposed partitioning divides the model and graph data so that R-GCN can be accelerated by using multiple GPUs. Also, the proposed approach can be applied to sequential execution on a single GPU. Both the cases can accelerate the R-GCN processing with large graph data, where the original model cannot be fit into a device memory of a single GPU without partitioning. Experimental results demonstrate that our partitioning method accelerates R-GCN by up to 3.28 times using four GPUs compared to CPU execution for a dataset with more than 1.6 million nodes and 5 million edges. Also, the proposed approach can accelerate the execution even with a single GPU by 1.55 times compared to the CPU execution for a dataset with 0.8 million nodes and 2 million edges.

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A unified accelerator design for LiDAR SLAM algorithms for low-end FPGAs

Sugiura K., Matsutani H.

2021 International Conference on Field-Programmable Technology, ICFPT 2021 (2021 International Conference on Field-Programmable Technology, ICFPT 2021) 2021

A fast and reliable LiDAR (Light Detection and Ranging) SLAM (Simultaneous Localization and Mapping) system is the growing need for autonomous mobile robots, which are used for a variety of tasks such as indoor cleaning, navigation, and transportation. To bridge the gap between the limited processing power on such robots and the high computational requirement of the SLAM system, in this paper we propose a unified accelerator design for 2D SLAM algorithms on resource-limited FPGA devices. As scan matching is the heart of these algorithms, the proposed FPGA-based accelerator utilizes scan matching cores on the programmable logic part and users can switch the SLAM algorithms to adapt to performance requirements and environments without modifying and re-synthesizing the logic part. We integrate the accelerator into two representative SLAM algorithms, namely particle filter-based and graph-based SLAM. They are evaluated in terms of resource utilization, processing speed, and quality of output results with various real-world datasets, highlighting their algorithmic characteristics. Experiment results on a Pynq-Z2 board demonstrate that scan matching is accelerated by 13.67-14.84x, improving the overall performance of particle filter-based and graph-based SLAM by 4.03-4.67x and 3.09-4.00x respectively, while maintaining the accuracy comparable to their software counterparts and even state-of-the-art methods.

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Traffic-independent multi-path routing for high-throughput data center networks

Kawano R., Yasudo R., Matsutani H., Koibuchi M., Amano H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E103D ( 12 ) 2471 - 2479 2020.12

ISSN 09168532

Network throughput has become an important issue for big-data analysis on Warehouse-Scale Computing (WSC) systems. It has been reported that randomly-connected inter-switch networks can enlarge the network throughput. For irregular networks, a multi-path routing method called k-shortest path routing is conventionally utilized. However, it cannot efficiently exploit longer-than-shortest paths that would be detour paths to avoid bottlenecks. In this work, a novel routing method called koptimized path routing to achieve high throughput is proposed for irregular networks. We introduce a heuristic to select detour paths that can avoid bottlenecks in the network to improve the average-case network throughput. Experimental results by network simulation show that the proposed k-optimized path routing can improve the saturation throughput by up to 18.2% compared to the conventional k-shortest path routing. Moreover, it can reduce the computation time required for optimization to 1/2760 at a minimum compared to our previously proposed method.

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A Selective Model Aggregation Approach in Federated Learning for Online Anomaly Detection

Qin Y., Matsutani H., Kondo M.

Proceedings - IEEE Congress on Cybermatics: 2020 IEEE International Conferences on Internet of Things, iThings 2020, IEEE Green Computing and Communications, GreenCom 2020, IEEE Cyber, Physical and Social Computing, CPSCom 2020 and IEEE Smart Data, SmartData 2020 (Proceedings - IEEE Congress on Cybermatics: 2020 IEEE International Conferences on Internet of Things, iThings 2020, IEEE Green Computing and Communications, GreenCom 2020, IEEE Cyber, Physical and Social Computing, CPSCom 2020 and IEEE Smart Data, SmartData 2020) 684 - 691 2020.11

ISSN 9781728176475

Cloud computing has established a convenient approach for computing offloading, where the data produced by edge devices is gathered and processed in a centralized server. However, it results in critical issues related to latency. Recently, a neural network-based on-device learning approach is proposed, which offers a solution to the latency problem by relocating processing data to edge devices; even so, a single edge device may face insufficient training data to train a high-quality model, because of its limited available processing capabilities and energy resources. To address this issue, we extend the work to a federated learning system which enables the edge devices to exchange their trained parameters and update local models. However, in federated learning for anomaly detection, the reliability of local models would be different. For example, a number of trained models are likely to contain the features of anomalous data because of noise corruption or anomaly detection failure. Besides, as the communication protocol amongst edges could be exploited by attackers, the training data or model weights may have potential risks of being poisoned. Therefore, when we design a federated training algorithm, we should carefully select the local models that participate in model aggregation. In this work, we leverage an observed dataset to compute prediction errors, so that the unsatisfying local models can be excluded from federated training. Experimental results show that the federated learning approach improves anomaly detection accuracy. Besides, the proposed model aggregation solution achieves obvious improvement compared with the popular Federated Averaging method.

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Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks

Kawano R., Matsutani H., Amano H.

Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020 (Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020) 93 - 99 2020.11

ISSN 9781728199191

As the scale of supercomputers has increased, the end-to-end network latency has become non-negligible on the performance of parallel applications. For this reason, low-latency network topologies achieving the smallest number of hops among switches are drawing attention. The Order/Degree Problem to find the topology with the smallest diameter has revealed that a topology based on graph symmetry and simulated annealing (SA) is optimal for a wide range of system sizes. Focusing on the characteristics of clustering and symmetry of this graph, we extend the method to guarantee the lower limit of the number of cables in each cabinet. The total cable length and cost can be minimized as well as minimizing the deterioration of communication delay. Compared with the conventional network topologies, the proposed network topology can attain higher performance with the smaller total cable length and cost.

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An In-Network Parameter Aggregation using DPDK for Multi-GPU Deep Learning

Furukawa M., Itsubo T., Matsutani H.

Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020 (Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020) 108 - 114 2020.11

ISSN 9781728182216

In distributed deep neural network using remote GPU nodes, communication occurs iteratively between remote nodes for gradient aggregation. This communication latency limits the benefit of distributed training with faster GPUs. In distributed deep learning using the remote GPUs, workload of gradient aggregation is imposed on a host machine. In this paper, we therefore propose to offload the gradient aggregation to a DPDK (Data Plane Development Kit) based network switch between the host machine and remote GPUs. In this approach, the aggregation process is completed in the network using extra computation resources in the network switch. We evaluate the proposed switch when GPUs and the host communicate with a standard IP communication and a PCI Express (PCIe) over 40Gbit Ethernet (40GbE) product, respectively. The evaluation results using a standard IP communication show that the aggregation is accelerated by 2.2-2.5x compared to the aggregation executed by a host machine. The results using the PCIe over 40GbE product show that the proposed switch outperforms the aggregation done by the host machine by 1.16x. This approach is thus useful for distributed training with multiple GPUs.

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Fast Semi-Supervised Anomaly Detection of Drivers' Behavior using Online Sequential Extreme Learning Machine

Oikawa H., Nishida T., Sakamoto R., Matsutani H., Kondo M.

2020 IEEE 23rd International Conference on Intelligent Transportation Systems, ITSC 2020 (2020 IEEE 23rd International Conference on Intelligent Transportation Systems, ITSC 2020) 2020.09

ISSN 9781728141497

With the wide spread of artificial intelligence (AI) technologies, many applications using AI are increasingly deployed in many fields. Specially anomaly detection is one of the key applications of AI. Among several targets, detecting anomaly behavior of drivers or vehicles has been attracting due to the growing demand of safety driving. It is crucial to study and evaluate techniques for anomaly driving detection with AI technologies. The Online Sequential Extreme Learning Machine (OS-ELM) is a recently attracting neural network model that has high memory efficiency and can perform highspeed sequential learning with streaming data. Though OSELM is known to be effective for anomaly detection, it has not yet been verified for non-stationary time series data such as driving sensor data. In this paper, we study the effectiveness of OS-ELM based anomaly driving behavior detector using sensor data of vehicles and compared the performance of it with a Hidden Markov Model (HMM) based and traditional Long Short-Term Memory (LSTM) based methods. Since the existing driving behavior benchmark data is not enough for evaluating anomaly driving, we also create a new dataset with a powered wheelchair. Throughout the evaluation, we show that the OS-ELM based anomaly driving detector has almost the same or even better accuracy in anomaly driving detection with much faster sequential learning speed compared with the HMM or LSTM based detector.

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In-GPU cache for acceleration of anomaly detection in blockchain

Morishima S., Matsutani H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E103D ( 8 ) 1814 - 1824 2020.08

ISSN 09168532

Blockchain is a distributed ledger system composed of a P2P network and is used for a wide range of applications, such as international remittance, inter-individual transactions, and asset conservation. In Blockchain systems, tamper resistance is enhanced by the property of transaction that cannot be changed or deleted by everyone including the creator of the transaction. However, this property also becomes a problem that unintended transaction created by miss operation or secret key theft cannot be corrected later. Due to this problem, once an illegal transaction such as theft occurs, the damage will expand. To suppress the damage, we need countermeasures, such as detecting illegal transaction at high speed and correcting the transaction before approval. However, anomaly detection in the Blockchain at high speed is computationally heavy, because we need to repeat the detection process using various feature quantities and the feature extractions become overhead. In this paper, to accelerate anomaly detection, we propose to cache transaction information necessary for extracting feature in GPU device memory and perform both feature extraction and anomaly detection in the GPU. We also propose a conditional feature extraction method to reduce computation cost of anomaly detection. We employ anomaly detection using K-means algorithm based on the conditional features. When the number of users is one million and the number of transactions is 100 millions, our proposed method achieves 8.6 times faster than CPU processing method and 2.6 times faster than GPU processing method that does not perform feature extraction on the GPU. In addition, the conditional feature extraction method achieves 1.7 times faster than the unconditional method when the number of users satisfying a given condition is 200 thousands out of one million.

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A neural network-based on-device learning anomaly detector for edge devices

Tsukada M., Kondo M., Matsutani H.

IEEE Transactions on Computers (IEEE Transactions on Computers) 69 ( 7 ) 1027 - 1044 2020.07

ISSN 00189340

Semi-supervised anomaly detection is an approach to identify anomalies by learning the distribution of normal data. Backpropagation neural networks (i.e., BP-NNs) based approaches have recently drawn attention because of their good generalization capability. In a typical situation, BP-NN-based models are iteratively optimized in server machines with input data gathered from the edge devices. However, (1) the iterative optimization often requires significant efforts to follow changes in the distribution of normal data (i.e., concept drift), and (2) data transfers between edge and server impose additional latency and energy consumption. To address these issues, we propose ONLAD and its IP core, named ONLAD Core. ONLAD is highly optimized to perform fast sequential learning to follow concept drift in less than one millisecond. ONLAD Core realizes on-device learning for edge devices at low power consumption, which realizes standalone execution where data transfers between edge and server are not required. Experiments show that ONLAD has favorable anomaly detection capability in an environment that simulates concept drift. Evaluations of ONLAD Core confirm that the training latency is 1.95x∼6.58x faster than the other software implementations. Also, the runtime power consumption of ONLAD Core implemented on PYNQ-Z1 board, a small FPGA/CPU SoC platform, is 5.0x∼25.4x lower than them.

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An Area-Efficient Implementation of Recurrent Neural Network Core for Unsupervised Anomaly Detection

Sakuma T., Matsutani H.

IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings) 2020.04

ISSN 9781728163475

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Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch

Itsubo T., Koibuchi M., Amano H., Matsutani H.

Proceedings - 2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2020 (Proceedings - 2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2020) 102 - 109 2020.03

ISSN 9781728165820

A back-propagation algorithm following a gradient descent approach is used for training deep neural networks. Since it iteratively performs a large number of matrix operations to compute the gradients, GPUs (Graphics Processing Units) are efficient especially for the training phase. Thus, a cluster of computers each of which equips multiple GPUs can significantly accelerate the training phase. Although the gradient computation is still a major bottleneck of the training, gradient aggregation and parameter optimization impose both communication and computation overheads, which should also be reduced for further shortening the training time. To address this issue, in this paper, multiple GPUs are interconnected with a PCI Express (PCIe) over 10 Gbit Ethernet (10GbE) technology. Since these remote GPUs are interconnected via network switches, gradient aggregation and optimizers (e.g., SGD, Adagrad, Adam, and SMORMS3) are offloaded to an FPGA-based network switch between a host machine and remote GPUs; thus, the gradient aggregation and optimization are completed in the network. Evaluation results using four remote GPUs connected via the FPGA-based 10GbE switch that implements the four optimizers demonstrate that these optimization algorithms are accelerated by up to 3. 0x and 1. 25x compared to CPU and GPU implementations, respectively. Also, the gradient aggregation throughput by the FPGA-based switch achieves 98.3% of the 10GbE line rate.

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A generalized theory based on the turn model for deadlock-free irregular networks

Kawano R., Yasudo R., Matsutani H., Koibuchi M., Amano H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E103D ( 1 ) 101 - 110 2020

ISSN 09168532

Recently proposed irregular networks can reduce the latency for both on-chip and off-chip systems with a large number of computing nodes and thus can improve the performance of parallel applications. However, these networks usually suffer from deadlocks in routing packets when using a naive minimal path routing algorithm. To solve this problem, we focus attention on a lately proposed theory that generalizes the turn model to maintain the network performance with deadlock-freedom. The theorems remain a challenge of applying themselves to arbitrary topologies including fully irregular networks. In this paper, we advance the theorems to completely general ones. Moreover, we provide a feasible implementation of a deadlock-free routing method based on our advanced theorem. Experimental results show that the routing method based on our proposed theorem can improve the network throughput by up to 138 % compared to a conventional deterministic minimal routing method. Moreover, when utilized as the escape path in Duato’s protocol, it can improve the throughput by up to 26.3 % compared with the conventional up*/down* routing.

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Designing low-diameter interconnection networks with multi-ported host-switch graphs

Yasudo R., Nakano K., Koibuchi M., Matsutani H., Amano H.

Concurrency Computation (Concurrency Computation) 2020

ISSN 15320626

A host-switch graph was originally proposed as a graph that represents a network topology of a computer systems with 1-port host computers and (Formula presented.) -port switches. It has been studied from both theoretical and practical aspects in terms of the diameter, the average shortest path length, and the performance of real applications. In recent high-performance computing systems, however, a host computer is connected to multiple switches by using InfiniBand, NVSwitch, or Omni-Path, and consequently they provide high bandwidths. Since a host-switch graph cannot represent such systems, this article extends a host-switch graph so that it can represent such systems. As a result, a host-switch graph can include multi-ported hosts. Furthermore, we propose to use multi-port hosts for reducing the diameter. We show that the diameter minimization is equivalent to solving the degree diameter problem for bipartite graphs of diameter three. Our experimental results show that we can drastically reduce the diameter as well as increasing the bandwidth and improves performance of MPI applications by up to 162% as compared with networks with single-ported hosts.

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Deadlock-free layered routing for infiniband networks

Kawano R., Matsutani H., Amano H.

Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019 (Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019) 84 - 90 2019.11

ISSN 9781728152684

End-to-end network latency has become an important issue for big data processing on large-scale and heterogeneous data centers. To realize them, a low-latency inter-switch network is required. In recent years, a novel network based on a random regular graph such as Jellyfish has been proposed as a solution to these problems. To realize this network on Infiniband, we explore layered shortest path routing that guarantees deadlock freedom. Infiniband can avoid deadlocks by using Virtual Lane (VL), which is a QoS guarantee mechanism. However, the output VL is indirectly determined by using Service Level (SL) held by each packet. In this research, to minimize the number of consumed SLs, we propose an algorithm based on a graph coloring problem to assign SLs to all source-destination pairs. The proposed method can reduce the number of consumed SLs by up to 38%compared to the conventional SL mapping method.

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An adaptive abnormal behavior detection using online sequential learning

Ito R., Tsukada M., Kondo M., Matsutani H.

Proceedings - 22nd IEEE International Conference on Computational Science and Engineering and 17th IEEE International Conference on Embedded and Ubiquitous Computing, CSE/EUC 2019 (Proceedings - 22nd IEEE International Conference on Computational Science and Engineering and 17th IEEE International Conference on Embedded and Ubiquitous Computing, CSE/EUC 2019) 436 - 440 2019.08

ISSN 9781728116631

In the real world, normal and abnormal behavior patterns vary depending on a given environment, which means that the abnormal behavior detection model should be customized. To address this issue, in this paper, we employ OS-ELM (Online Sequential Extreme Learning Machine) and Autoencoder for adaptive abnormal behavior detection. First, state-transition probability tables of a target during an initial learning period are learned as normal behaviors. Then, Autoencoder-based anomaly detection is performed for the state-transition probability tables of subsequent time frames. The abnormal behavior detection model is updated by using OS-ELM algorithm every time a new probability table or behavior comes. The number of abnormal behavior detection instances is dynamically tuned to reflect the recent normal patterns or modes. Also, the table is compressed to reduce the computation cost. Evaluation results using a driving dataset of cars show that the proposed abnormal behavior detection accurately identifies normal and aggressive driving patterns with the optimal number of the abnormal behavior detection instances.

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Sparse 3-D NoCs with Inductive Coupling

Michihiro Koibuchi, Lambert Leong, Tomohiro Totoki, Naoya Niwa, Hiroki Matsutani, Hideharu Amano, Henri Casanova

Design Automation Conference (DAC'19) (Proceedings - Design Automation Conference) 2019.06

Research paper (international conference proceedings), Joint Work, Accepted, ISSN 9781450367257

Wireless interconnects based on inductive coupling technology are compelling propositions for designing 3-D integrated chips. This work addresses the heat dissipation problem on such systems. Although effective cooling technologies have been proposed for systems designed based on Through Silicon Via (TSV), their application to systems that use inductive coupling is problematic because of increased wireless-communication distance. For this reason, we propose two methods for designing sparse 3-D chips layouts and Networks on Chip (NoCs) based on inductive coupling. The first method computes an optimized 3-D chip layout and then generates a randomized network topology for this layout. The second method uses a standard stack chip layout with a standard network topology as a starting point, and then deterministically transforms it into either a "staircase" or a "checkerboard" layout. We quantitatively compare the designs produced by these two methods in terms of network and application performance. Our main finding is that the first method produces designs that ultimately lead to higher parallel application performance, as demonstrated for nine OpenMP applications in the NAS Parallel Benchmarks.

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Performance and Cost Evaluations of Online Sequential Learning and Unsupervised Anomaly Detection Core

Itsubo T., Tsukada M., Matsutani H.

IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings) 2019.05

ISSN 9781728117485

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Key-value Store Chip Design for Low Power Consumption

Tokusashi Y., Matsutani H., Amano H.

IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings) 2019.05

ISSN 9781728117485

Low-power embedded systems often require simple but flexible functionality for data management. Key-value store is one of data stores, which provides simple API and is easy to scale-out. We developed a dedicated key-value store core as a low-power embedded storage. In this paper, key-value store chip is fabricated with Renesas SOTB 65-nm process technology. We evalute the real chip in terms of power consumption and operating frequency by tuning VDD and body bias voltage. The chip achieved 11.2mW as power consumption with 0.7V VDD if the target frequency is 40MHz. When data rate is low, the system can reduce power consumption by tuning VDD and body bias voltage.

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Network optimizations on prediction server with multiple predictors

Okuyama K., Tokusashi Y., Iwata T., Tsukada M., Kishiki K., Matsutani H.

Proceedings - 16th IEEE International Symposium on Parallel and Distributed Processing with Applications, 17th IEEE International Conference on Ubiquitous Computing and Communications, 8th IEEE International Conference on Big Data and Cloud Computing, 11th IEEE International Conference on Social Computing and Networking and 8th IEEE International Conference on Sustainable Computing and Communications, ISPA/IUCC/BDCloud/SocialCom/SustainCom 2018 (Proceedings - 16th IEEE International Symposium on Parallel and Distributed Processing with Applications, 17th IEEE International Conference on Ubiquitous Computing and Communications, 8th IEEE International Conference on Big Data and Cloud Computing, 11th IEEE International Conference on Social Computing and Networking and 8th IEEE International Conference on Sustainable Computing and Communications, ISPA/IUCC/BDCloud/SocialCom/SustainCom 2018) 1044 - 1045 2019.03

ISSN 9781728111414

Toward machine learning based prediction services, the prediction server has multiple predictors and selects an appropriate one based on past feedbacks from the clients. In this case, three messages including request, reply, and feedback, are required for each prediction request. Packets are typically transmitted and received via a network protocol stack in OS kernel, and performance improvement can be expected by avoiding the protocol stack since it degrades the communication performance especially for small packets. We implement the prediction server using network optimization approaches including kernel-bypassing and in-NIC processing approaches. Evaluation results show that these network optimizations are beneficial to improve the prediction server performance compared to a baseline prediction server using a standard network protocol stack.

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Accelerating blockchain transfer system using FPGA-Based NIC

Sakakibara Y., Tokusashi Y., Morishima S., Matsutani H.

ISSN 9781728111414

Blockchain is core technology for cryptocurrency and it is possible to become fundamental platform for industry and business. Especially, a blockchain-based digital asset transfer system using Internet of Things (IoT) products has recently been considered as a new practical platform, but the protocol limits performance. Previous research has improved performance by proposing new protocols, but further improvement is necessary for dealing with increasing transactions via IoT products. Therefore, we propose an in-Network Interface Card (in-NIC) processing approach using a Field Programmable Gate Array (FPGA) to improve performance of a blockchain-based transfer system. To be more concrete, we design and implement a prototype NIC with a key-value data store written in a P4 language on the FPGA that has four 10Gigabit Ethernet (10GbE) network interfaces. The prototype system supports frequently-used commands (CREATE, ISSUE, TRANSFER and REFER) for transferring digital asset. It reduces time for processing a kernel network protocol stack and accessing the data store. In fact, we measured throughput and latency of our prototype system compared to those of a blockchain software application. As a result, we found that our solution is able to obtain throughput 6.04 times higher on average and latency 15.4 times lower on average for all typical blockchain operations.

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Acceleration of anomaly detection in blockchain using in-GPU Cache

Morishima S., Matsutani H.

ISSN 9781728111414

Blockchain is a distributed ledger system composed of a P2P network and is used for a wide range of applications, such as international remittance, inter-individual transactions, and asset conservation. In Blockchain systems, tamper resistance is enhanced by the property of transaction that cannot be changed or deleted by everyone including the creator of the transaction. However, this property also becomes a problem that unintended transaction created by miss operation or secret key theft cannot be corrected later. Due to this problem, once an illegal transaction such as theft occurs, the damage will expand. To suppress the damage, we need countermeasures, such as detecting illegal transaction at high speed and correcting the transaction before approval. However, abnormality detection in the Blockchain at high speed is computationally heavy, because we need to repeat the detection process using various feature quantities and the feature extractions become overhead. In this paper, to accelerate abnormality detection, we propose to cache transaction information necessary for extracting feature in GPU device memory and perform both feature extraction and abnormality detection in the GPU. We employ abnormality detection using K-means algorithm based on the conditional features. When the number of users is one million and the number of transactions is 100 millions, our proposed method achieves 37.1 times faster than CPU processing method and 16.1 times faster than GPU processing method that does not perform feature extraction on the GPU.

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LaKe: The power of in-network computing

Tokusashi Y., Matsutani H., Zilberman N.

2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018 (2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018) 2019.02

ISSN 9781728119687

In-network computing accelerates applications natively running on the host by executing them within network devices. While in-network computing offers significant performance improvements, its limitations and design trade-offs have not been explored. To usefully and efficiently run applications within the network, we first need to understand the implications of their design. In this work we introduce LaKe, a Layered Key-Value Store design, running as an in-network application. LaKe is a scalable design, enabling the exploration of design decisions and their effect on throughput, latency and power efficiency. LaKe achieves full line rate throughput, while maintaining a latency of 1.1 μs and better power efficiency than existing hardware based memcached designs.

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Designing High-Performance Interconnection Networks with Host-Switch Graphs

Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano

IEEE Transactions on Parallel and Distributed Systems (TPDS) (IEEE Transactions on Parallel and Distributed Systems) 30 ( 2 ) 315 - 330 2019.02

Research paper (scientific journal), Joint Work, Accepted, ISSN 10459219

This paper aims at establishing a method for designing high-performance network topologies to bridge a gap between theoretical and practical studies. To this end, we present a novel graph called a host-switch graph, which consists of host vertices and switch vertices with maximum degree 1 and r, respectively. This graph represents a network topology of a practical parallel/distributed computer system with host computers connected by r-port switches. We discuss important metrics for designing high-performance interconnection networks: the host-to-host average shortest path length (h-ASPL) and the bisection width (BiW). In particular, we explore a method for constructing host-switch graphs with low h-ASPL and high BiW that connect the fixed number of hosts via any number of r-port switches. We demonstrate that the number of switches that provides the minimum h-ASPL can mathematically be approximated, and the minimum number of switches that provides a certain BiW can experimentally be approximated. On the basis of the approximations, we propose a randomized algorithm for searching host-switch graphs. We then apply the graphs to interconnection networks and compare them with typical network topologies. As compared with the torus, the dragonfly, and the fat-tree, our networks attain higher performance and smaller power and costs.

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OS-ELM-FPGA: An FPGA-based online sequential unsupervised anomaly detector

Tsukada M., Kondo M., Matsutani H.

ISSN 9783030105488

Autoencoder, a neural-network based dimensionality reduction algorithm has demonstrated its effectiveness in anomaly detection. It can detect whether an input sample is normal or abnormal by just training only with normal data. In general, Autoencoder is built on backpropagation-based neural networks (BP-NNs). When BP-NNs are implemented in edge devices, they are typically specialized only for prediction with weight matrices precomputed offline due to the high computational cost. However, such devices cannot be immediately adapted to time-series trend changes of input data. In this paper, we propose an FPGA-based unsupervised anomaly detector, called OS-ELM-FPGA, that combines Autoencoder and an online sequential learning algorithm OS-ELM. Based on our theoretical analysis of the algorithm, the proposed OS-ELM-FPGA completely eliminates matrix pseudoinversions while improving the learning throughput. Simulation results using open-source datasets show that OS-ELM-FPGA achieves favorable anomaly detection accuracy compared to CPU and GPU implementations of BP-NNs. Learning throughput of OS-ELM-FPGA is 3.47x to 27.99x and 5.22x to 78.06x higher than those of CPU and GPU implementations of OS-ELM. It is also 3.62x to 36.15x and 1.53x to 43.44x higher than those of CPU and GPU implementations of BP-NNs.

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Accelerating online change-point detection algorithm using 10 GbE FPGA NIC

Iwata T., Nakamura K., Tokusashi Y., Matsutani H.

ISSN 9783030105488

In statistical analysis and data mining, change-point detection that identifies the change-points which are times when the probability distribution of time series changes has been used for various purposes, such as anomaly detections on network traffic and transaction data. However, computation cost of a conventional AR (Auto-Regression) model based approach is too high and infeasible for online. In this paper, an AR model based online change-point detection algorithm, called ChangeFinder, is implemented on an FPGA (Field Programmable Gate Array) based NIC (Network Interface Card). The proposed system computes the change-point score from time series data received from 10 GbE (10 Gbit Ethernet). More specifically, it computes the change-point score at the 10 GbE NIC in advance of host applications. This paper aims to reduce the host workload and improve change-point detection performance by offloading ChangeFinder algorithm from host to the NIC. As evaluations, change-point detection in the FPGA NIC is compared with a baseline software implementation and those enhanced by two network optimization techniques using DPDK and Netfilter in terms of throughput. The result demonstrates 16.8x improvement in change-point detection throughput compared to the baseline software implementation. The throughput achieves 83.4% of the 10 GbE line rate.

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An FPGA-based change-point detection for 10Gbps packet stream

Iwata T., Nakamura K., Tokusashi Y., Matsutani H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E102D ( 12 ) 2366 - 2376 2019

ISSN 09168532

In statistical analysis and data mining, change-point detection that identifies the change-points which are times when the probability distribution of time series changes has been used for various purposes, such as anomaly detections on network traffic and transaction data. However, computation cost of a conventional AR (Auto-Regression) model based approach is too high and infeasible for online. In this paper, an AR model based online change-point detection algorithm, called ChangeFinder, is implemented on an FPGA (Field Programmable Gate Array) based NIC (Network Interface Card). The proposed system computes the change-point score from time series data received from 10GbE (10Gbit Ethernet). More specifically, it computes the change-point score at the 10GbE NIC in advance of host applications. It can find change-points on single or multiple streams using a context memory. This paper aims to reduce the host workload and improve change-point detection performance by offloading ChangeFinder algorithm from host to the NIC. As evaluations, change-point detection in the FPGA NIC is compared with a baseline software implementation and those enhanced by two network optimization techniques using DPDK and Netfilter in terms of throughput. The result demonstrates 16.8x improvement in change-point detection throughput compared to the baseline software implementation. It is corresponding to the 10GbE line rate. Performance and area overheads when supporting multiple streams are also evaluated.

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K-Optimized Path Routing for High-Throughput Data Center Networks

Kawano R., Yasudo R., Matsutani H., Amano H.

Proceedings - 2018 6th International Symposium on Computing and Networking, CANDAR 2018 (Proceedings - 2018 6th International Symposium on Computing and Networking, CANDAR 2018) 99 - 105 2018.12

ISSN 9781538691823

Network throughput has become an important issue for big-data analysis on Warehouse-Scale Computing (WSC) systems. It has been reported that randomly-connected inter-switch networks can enlarge the network throughput. For irregular networks, a multi-path routing method called k-shortest path routing is conventionally utilized. However, it cannot efficiently exploit longer-than-shortest paths that would be detour paths to avoid bottlenecks. In this work, a novel routing method called k-optimized path routing to achieve high throughput is proposed for irregular networks. We introduce a heuristic to select detour paths that can avoid bottlenecks in the network to improve the network throughput. Experimental results show that the proposed k-optimized path routing can improve the throughput by up to 133 % compared to the conventional k-shortest path routing. Moreover, it can improve the network bandwidth while maintaining the low network latency.

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An trace-driven performance prediction method for exploring noc design optimization

Niwa N., Totoki T., Matsutani H., Koibuchi M., Amano H.

Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018 (Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018) 182 - 185 2018.12

ISSN 9781538691847

The performance prediction for a NoC-based Chip Multi-Processor (CMP) is one of the main design concerns. Generally, there is a trade-off between accuracy and time overhead on the performance prediction of computer systems. In particular, the time overhead is proportional or exponential to the number of cores when using a cycle-accurate full-system simulation, such as gem5. In this study, we propose an accurate and scalable method to predict the influence of design NoC parameters on its performance. Our method counts the number of execution cycles when employing the target NoC based on the statistics of one-time execution of a full-system simulation using a fully-connected NoC. To evaluate the accuracy and execution time overhead, we use the case that randomly generates allocations of processors with 3D mesh topology NoC. Its Mean Absolute Percentage Error of the estimated cycles is about 4.7%, and the Maximum Absolute Percentage Error is about 8.5%.

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MultiMQC: A Multilevel Message Queuing Cache Combining In-NIC and In-Kernel Memories

Koya Mitsuzuka, Yuta Tokusashi, Hiroki Matsutani

International Conference on Field Programmable Technology (FPT'18) (Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018) 137 - 144 2018.12

Research paper (international conference proceedings), Joint Work, Accepted, ISSN 9781728102139

Message queuing systems that deliver messages from publishers to subscribers play an important role to collect data from IoT devices. Traditional message queuing systems have improved their performance in the context of transferring log data from publishers such as Web servers to subscribers that analyze the log data. In this case, both publishers and subscribers have been assumed to have enough buffer capacity and can transfer data as jumbo frame packets for high efficiency. In recent IoT applications, however, publishers are small sensors or edge devices with low-power processors and limited memory capacity. Vast numbers of such publishers produce relatively small packets. Such a lot of small messages significantly decrease the efficiency of conventional message queuing systems. To address this issue, a dedicated message queuing logic can be implemented on FPGA-based network interface card (FPGA NIC). However, a serious issue of such in-NIC approach is a limited memory capacity on the FPGA NIC. To handle message overflow of the in-NIC cache, in this paper, it is combined with a large in-kernel software cache. More specifically, we propose a multilevel message queuing cache combining in-NIC and in-kernel memories, called MultiMQC. The multilevel cache improves the read performance. Regarding the write performance, MultiMQC introduces a batch transfer that packs small incoming messages into a single batch. We implemented MultiMQC using NetFPGA-SUME board as in-NIC cache and Linux Netfilter framework as in-kernel cache. The experimental results demonstrate that the write throughput is increased in proportion to the batch size. When pull requests hit in the in-NIC cache, the read throughput reaches 95.8% of 10GbE line rate in four 10GbE interfaces.

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Low-reliable low-latency networks optimized for HPC parallel applications

Nguyen T., Matsutani H., Koibuchi M.

NCA 2018 - 2018 IEEE 17th International Symposium on Network Computing and Applications (NCA 2018 - 2018 IEEE 17th International Symposium on Network Computing and Applications) 2018.11

ISSN 9781538676592

High-end network standards, such as 400GbE, have been introduced Forwarding Error Correction (FEC) for maintaining the same bit error rate (BER) as that in traditional low-bandwidth interconnection networks. However, FEC operation latency overhead surprisingly becomes higher than the sum of all the other switch operation overheads, e.g., routing computation and switch allocation. FEC operation latency overhead significantly degrades the performance of parallel applications in HPC systems. Instead, in this study, we exploit the low-latency network design using a Hamming code that does not provide rigid error-free communication. Since it is consistent with existing frame format based on standard Reed-Solomon RS(544,514) with DC(64b/66b) direct linecode and TC(256b/257b) transcode, respectively, the influences upon the other network layer design are limited. Interestingly, a large number of parallel applications can accept the BER in such a Hamming code. Since lowering such a BER improves switch operation latency, the proposed network using the Hamming code improves the execution time of NAS Parallel Benchmarks by 56% on average when compared to the counterpart RS-FEC networks.

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Adaptive body bias control scheme for ultra low-power network-on-chip systems

Ben Ahmed A., Okuhara H., Matsutani H., Koibuchi M., Amano H.

Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018 (Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018) 146 - 153 2018.11

ISSN 9781538666890

Over the past decade, the power consumption has been one of the main design challenges in Network-on-Chips (NoCs) as it significantly defines the performance of a given Chip-Multiprocessor (CMP). Body bias control is one of the solutions that provide an efficient trade-off between leakage power and performance. However, employing such a method is not straightforward since several factors should be taken into consideration, especially when adaptively implemented on-chip. In this paper, we propose a new router design and on-chip body bias control mechanism to adaptively control the body bias voltages supply in ultra low-power NoC systems. With the help of a light-weight monitoring circuit, the proposed router predicts the traffic load at each input-port and accordingly adjusts its pipeline depth in a fine-grained fashion. To satisfy the timing constraints, the router adaptively supplies each one of its input-ports with the appropriate body bias voltages to either boost the performance or to reduce the leakage power at the standby state. The evaluation results, using the SOTB 65nm Fully Depleted Silicon On Insulator (FD-SOI) technology, shows the ability of the proposed router in reducing both dynamic and static energies. When compared to two fixed-pipeline baseline routers (3-stages and 2-stages), the total energy reduction could reach up to 67% and 59%, respectively. At the same time, a reasonable performance tendency can be obtained with less than 6% area overhead.

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AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation

Akram Ben Ahmed, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

International Symposium on Networks-on-Chip (NOCS'18) (2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018) 1 - 8 2018.10

Research paper (international conference proceedings), Joint Work, Accepted, ISSN 9781538648933

Various parallel applications, such as numerical convergent computation and multimedia processing, have intrinsic tolerance to inaccuracies that allow soft errors, i.e. bit flips, on a chip. However, existing Network-on-Chips (NoCs) guarantee error-free data transfer; thus, encountering limits to reduce the power consumption. In this context, we propose an approximate dual-voltage NoC, called AxNoC. An AxNoC router uses a per-flit look-ahead power management so that headers and important-data flits are perfectly transferred at a high voltage while the remaining flits may incur bit flips by decreasing the supply voltage. An AxNoC router isolates the critical path when the supply voltage is low since such a critical path is enabled only at high voltage. The critical path isolation enables low-voltage operation to work at the same operating frequency at high voltage. An AxNoC router was implemented using a 28nm process and the evaluation results illustrate its efficiency to reduce the power consumption reaching up to 43% while incurring a small area overhead that does not exceed 6.2%. We also demonstrate that AxNoC exhibits an acceptable accuracy illustrated in a sufficiently small geomean of error.

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Proxy responses by FPGA-based switch for MapReduce stragglers

Mitsuzuka K., Koibuchi M., Amano H., Matsutani H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E101D ( 9 ) 2258 - 2268 2018.09

ISSN 09168532

In parallel processing applications, a few worker nodes called "stragglers", which execute their tasks significantly slower than other tasks, increase the execution time of the job. In this paper, we propose a network switch based straggler handling system to mitigate the burden of the compute nodes. We also propose how to offload detecting stragglers and computing their results in the network switch with no additional communications between worker nodes. We introduce some approximate techniques for the proxy computation and response at the switch; thus our switch is called "ApproxSW." As a result of a simulation experiment, the proposed approximation based on task similarity achieves the best accuracy in terms of quality of generated Map outputs. We also analyze how to suppress unnecessary proxy computation by the ApproxSW. We implement ApproxSW on NetFPGA-SUME board that has four 10Gbit Ethernet (10GbE) interfaces and a Virtex-7 FPGA. Experimental results shows that the ApproxSW functions do not degrade the original 10GbE switch performance.

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Accelerating Blockchain Search of Full Nodes Using GPUs

Morishima S., Matsutani H.

Proceedings - 26th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2018 (Proceedings - 26th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2018) 244 - 248 2018.06

ISSN 9781538649756

Blockchain is a distributed ledger system based on P2P network and originally used for a crypto currency system. The P2P network of Blockchain is maintained by full nodes which are in charge of verifying all the transactions in the network. However, most Blockchain user nodes do not act as full nodes, because workload of full nodes is quite high for personal mobile devices. Blockchain search queries, such as confirming balance, transaction contents, and transaction histories, from many users go to the full nodes. As a result, search throughput of full nodes would be a new bottleneck of Blockchain system, because the number of full nodes is less than the number of users of Blockchain systems. In this paper, we propose an acceleration method of Blockchain search using GPUs. More specifically, we introduce an array-based Patricia tree structure suitable for GPU processing so that we can make effective use of Blockchain feature that there are no update and delete queries. In the evaluations, the proposed method is compared with an existing GPU-based key-value search and a conventional CPU-based search in terms of the throughput of Blockchain key search. As a result, the throughput of our proposal is 3.4 times higher than that of the existing GPU-based search and 14.1 times higher than that of the CPU search when the number of keys is 80 ×220 and the key length is 256-bit in Blockchain search queries.

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Special session on bringing cores closer together: The wireless revolution in on-chip communication

Mak T., Matsutani H., Pande P.P.

Proceedings of the IEEE VLSI Test Symposium (Proceedings of the IEEE VLSI Test Symposium) 2018-April 2018.05

ISSN 9781538637746

The emerging field of NoC with Wireless interconnects is actively being pursued by a number of researchers worldwide, from a variety of different perspectives, ranging from very high levels of abstraction (e.g., system architecture) to very low levels (physical layer and transceiver design). Successful solutions will likely adopt and encompass elements from all or at least several levels of abstraction and rely on interdisciplinary concepts from multi-core architectures, integrated circuits, 3D ICs, digital communications, complex networks, and optimization techniques. This special session will provide a timely and insightful journey into various challenges and emerging solutions regarding the design of future NoC architectures. By scope and contents, this special session represents an engaging proposition to attendees belonging to both academia and industry.

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Building block multi-chip systems using inductive coupling through chip interface

Amano H., Kuroda T., Nakamura H., Usami K., Kondo M., Matsutani H., Namiki M.

Proceedings - International SoC Design Conference 2017, ISOCC 2017 (Proceedings - International SoC Design Conference 2017, ISOCC 2017) 152 - 154 2018.05

ISSN 9781538622858

A building block computing system is consisting of multiple chips connecting with inductive coupling wireless through chip interconnect. Like building Lego blocks, various types of systems can be built by stacking different types of chips. In order to develop such systems, several techniques are investigated in the project: that is, inductive coupling wireless through chip interface, low power circuit technologies, autonomous interconnection network architectures, thermal dissipation and building block operating system. Here, the overview of the project and a prototype system are introduced.

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A hardware-based caching system on FPGA NIC for Blockchain

Sakakibara Y., Morishima S., Nakamura K., Matsutani H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E101D ( 5 ) 1350 - 1360 2018.05

ISSN 09168532

Engineers and researchers have recently paid attention to Blockchain. Blockchain is a fault-tolerant distributed ledger without administrators. Blockchain is originally derived from cryptocurrency, but it is possible to be applied to other industries. Transferring digital asset is called a transaction. Blockchain holds all transactions, so the total amount of Blockchain data will increase as time proceeds. On the other hand, the number of Internet of Things (IoT) products has been increasing. It is difficult for IoT products to hold all Blockchain data because of their storage capacity. Therefore, they access Blockchain data via servers that have Blockchain data. However, if a lot of IoT products access Blockchain network via servers, server overloads will occur. Thus, it is useful to reduce workloads and improve throughput. In this paper, we propose a caching technique using a Field Programmable Gate Array-based (FPGA) Network Interface Card (NIC) which possesses four 10Gigabit Ethernet (10GbE) interfaces. The proposed system can reduce server overloads, because the FPGA NIC instead of the server responds to requests from IoT products if cache hits. We implemented the proposed hardware cache to achieve high throughput on NetFPGA-10G board. We counted the number of requests that the server or the FPGA NIC processed as an evaluation. As a result, the throughput improved by on average 1.97 times when hitting the cache.

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High-Performance with an In-GPU Graph Database Cache

Shin Morishima, Hiroki Matsutani

IEEE IT Professional 19 ( 6 ) 58 - 64 2017.12

Research paper (scientific journal), Joint Work, Accepted

HiRy: An Advanced Theory on Design of Deadlock-free Adaptive Routing for Arbitrary Topologies

Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

International Conference on Parallel and Distributed Systems (ICPADS'17) (Proceedings of the International Conference on Parallel and Distributed Systems - ICPADS) 2017-December 664 - 673 2017.12

Research paper (international conference proceedings), Joint Work, Accepted, ISSN 9781538621295

Recently proposed irregular networks can reduce the latency for both on-chip and off-chip systems with a large number of computing nodes and thus can improve the performance of parallel application. However, these networks usually suffer from deadlocks in routing packets when using a naive minimal path routing algorithm. To solve this problem, we focus attention on a lately proposed theory that generalizes the turn model to maintain the network performance with deadlock-freedom. The theorems remain a challenge of applying themselves to arbitrary topologies including fully irregular networks. In this paper, we advance the theorems to completely general ones. To apply the idea of the turn model to arbitrary topologies, we introduce a concept of regions that define continuous directions of channels on an n-dimensional space. Moreover, we provide a feasible implementation of a deadlock-free routing method based on our advanced theorem. To reduce the latency and the number of required Virtual Channels (VCs) with this method, a heuristic approach is introduced to reduce the number of prohibited turns between channels. Experimental results show that the routing method based on our proposed theorem can improve the network throughput by up to 138 % compared to a conventional deterministic minimal routing method. Moreover, it can reduce the latency by up to 2.9 % compared to another fully adaptive routing method.

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Multilevel NoSQL Cache Combining In-NIC and In-Kernel Approaches

Yuta Tokusashi, Hiroki Matsutani

IEEE Micro 37 ( 5 ) 44 - 51 2017.10

Research paper (scientific journal), Joint Work, Accepted

A Case for Uni-Directional Network Topologies in Large-Scale Clusters

Michihiro Koibuchi, Tomohiro Totoki, Hiroki Matsutani, Hideharu Amano, Fabien Chaix, Ikki Fujiwara, Henri Casanova

International Conference on Cluster Computing (Cluster'17) 178 - 187 2017.09

Research paper (international conference proceedings), Joint Work, Accepted

Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks

Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano

International Conference on Parallel Processing (ICPP'17) 322 - 331 2017.08

Research paper (international conference proceedings), Joint Work, Accepted

Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers

Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura

IEEE Transactions on Computers (TC) 66 ( 4 ) 702 - 716 2017.04

Research paper (scientific journal), Joint Work, Accepted

An FPGA-Based In-NIC Cache Approach for Lazy Learning Outlier Filtering

Ami Hayashi, Hiroki Matsutani

International Conference on Parallel, Distributed, and Network-Based Processing (PDP'17) 15 - 22 2017.03

Research paper (international conference proceedings), Joint Work, Accepted

High-Bandwidth Low-Latency Approximate Interconnection Networks

Daichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi

IEEE International Symposium on High-Performance Computer Architecture (HPCA'17) 469 - 480 2017.02

Research paper (international conference proceedings), Joint Work, Accepted

Accelerating Spark RDD Operations with Local and Remote GPU Devices

Yasuhiro Ohno, Shin Morishima, Hiroki Matsutani

International Conference on Parallel and Distributed Systems (ICPADS'16) 791 - 799 2016.12

Research paper (international conference proceedings), Joint Work, Accepted

Randomly Optimized Grid Graph for Low-Latency Interconnection Networks

Koji Nakano, Daisuke Takafuji, Satoshi Fujita, Hiroki Matsutani, Ikki Fujiwara, Michihiro Koibuchi

International Conference on Parallel Processing (ICPP'16) 340 - 349 2016.08

Research paper (international conference proceedings), Joint Work, Accepted

A Multilevel NOSQL Cache Design Combining In-NIC and In-Kernel Caches

Yuta Tokusashi, Hiroki Matsutani

IEEE International Symposium on High Performance Interconnects (Hot Interconnects 24) 60 - 67 2016.08

Research paper (international conference proceedings), Joint Work, Accepted

Randomizing Packet Memory Networks for Low-latency Processor-memory Communication

Daichi Fujiki, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi

International Conference on Parallel, Distributed, and Network-Based Processing (PDP'16) 168 - 175 2016.02

Research paper (international conference proceedings), Joint Work, Accepted

Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces

Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano

IEEE Transactions on Very Large Scale Integration Systems (TVLSI) 24 ( 2 ) 493 - 506 2016.02

Research paper (scientific journal), Joint Work, Accepted

A Line Rate Outlier Filtering FPGA NIC using 10GbE Interface

Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani

ACM SIGARCH Computer Architecture News (CAN) 43 ( 4 ) 22 - 27 2015.09

Research paper (scientific journal), Joint Work, Accepted

On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck

Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura

ACM/IEEE International Symposium on Networks-on-Chip (NOCS'15) 16:1 - 16:8 2015.09

Research paper (international conference proceedings), Joint Work, Accepted

Swap-and-randomize: A Method for Building Low-latency HPC Interconnects

Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova

IEEE Transactions on Parallel and Distributed Systems (TPDS) 26 ( 7 ) 2051 - 2060 2015.07

Research paper (scientific journal), Joint Work, Accepted

Augmenting Low-latency HPC Network with Free-space Optical Links

Ikki Fujiwara, Michihiro Koibuchi, Tomoya Ozaki, Hiroki Matsutani, Henri Casanova

IEEE International Symposium on High-Performance Computer Architecture (HPCA'15) 390 - 401 2015.02

Research paper (international conference proceedings), Joint Work, Accepted

Performance Evaluations of Graph Database using CUDA and OpenMP-Compatible Libraries

Shin Morishima, Hiroki Matsutani

ACM SIGARCH Computer Architecture News (CAN) 42 ( 4 ) 75 - 80 2014.09

Research paper (scientific journal), Joint Work, Accepted

Skywalk: a Topology for HPC Networks with Low-delay Switches

Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova

IEEE International Parallel and Distributed Processing Symposium (IPDPS'14) 263 - 272 2014.05

Research paper (international conference proceedings), Joint Work, Accepted

Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips

Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano

Design, Automation, and Test in Europe Conference (DATE'14) 1 - 6 2014.03

Research paper (international conference proceedings), Joint Work, Accepted

3-D NoC with Inductive-Coupling Links for Building-Block SiPs

Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano

IEEE Transactions on Computers (TC) 63 ( 3 ) 748 - 763 2014.03

Research paper (scientific journal), Joint Work, Accepted

A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface

Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura

IEEE Micro 33 ( 6 ) 6 - 15 2013.12

Research paper (scientific journal), Joint Work, Accepted

Headfirst Sliding Routing: A Time-Based Routing Scheme for Bus-NoC Hybrid 3-D Architecture

Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

ACM/IEEE International Symposium on Networks-on-Chip (NOCS'13) 29 - 36 2013.04

Research paper (international conference proceedings), Joint Work, Accepted

Layout-conscious Random Topologies for HPC Off-chip Interconnects

Michihiro Koibuchi, Ikki Fujiwara, Hiroki Matsutani, Henri Casanova

IEEE International Symposium on High-Performance Computer Architecture (HPCA'13) 484 - 495 2013.02

Research paper (international conference proceedings), Joint Work, Accepted

A Case for Wireless 3D NoCs for CMPs

Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano

Asia and South Pacific Design Automation Conference (ASP-DAC'13) 23 - 28 2013.01

Research paper (international conference proceedings), Joint Work, Accepted

Dependable Responsive Multithreaded Processor for Distributed Real-Time Systems

Kazutoshi Suito, Rikuhei Ueda, Kei Fujii, Takuma Kogo, Hiroki Matsutani, Nobuyuki Yamasaki

IEEE Micro 32 ( 6 ) 52 - 61 2012.12

Research paper (scientific journal), Joint Work, Accepted

A Case for Random Shortcut Topologies for HPC Interconnects

Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova

ACM/IEEE International Symposium on Computer Architecture (ISCA'12) 177 - 188 2012.06

Research paper (international conference proceedings), Joint Work, Accepted

A Multi-Vdd Dynamic Variable-Pipeline On-Chip Router for CMPs

Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano

Asia and South Pacific Design Automation Conference (ASP-DAC'12) 407 - 412 2012.01

Research paper (international conference proceedings), Joint Work, Accepted

Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors

Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga

IEEE Transactions on Computers (TC) 60 ( 6 ) 783 - 799 2011.06

Research paper (scientific journal), Joint Work, Accepted

A Vertical Bubble Flow Network using Inductive-Coupling for 3-D CMPs

Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano

ACM/IEEE International Symposium on Networks-on-Chip (NOCS'11) 49 - 56 2011.05

Research paper (international conference proceedings), Joint Work, Accepted

Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs

Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 30 ( 4 ) 520 - 533 2011.04

Research paper (scientific journal), Joint Work, Accepted

Ultra Fine-Grained Run-Time Power Gating of On-Chip Routers for CMPs

Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano

ACM/IEEE International Symposium on Networks-on-Chip (NOCS'10) 61 - 68 2010.05

Research paper (international conference proceedings), Joint Work, Accepted

MuCCRA-Cube: a 3D Dynamically Reconfigurable Processor with Inductive-Coupling Link

Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano

International Conference on Field Programmable Logic and Applications (FPL'09) 6 - 11 2009.09

Research paper (international conference proceedings), Joint Work, Accepted

Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network

Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano

IEEE Transactions on Parallel and Distributed Systems (TPDS) 20 ( 8 ) 1126 - 1141 2009.08

Research paper (scientific journal), Joint Work, Accepted

An On/Off Link Activation Method for Low-Power Ethernet in PC Clusters

Michihiro Koibuchi, Tomohiro Otsuka, Hiroki Matsutani, Hideharu Amano

IEEE International Parallel and Distributed Processing Symposium (IPDPS'09) 1 - 11 2009.05

Research paper (international conference proceedings), Joint Work, Accepted

Prediction Router: Yet Another Low Latency On-Chip Router Architecture

Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga

IEEE International Symposium on High-Performance Computer Architecture (HPCA'09) 367 - 378 2009.02

Research paper (international conference proceedings), Joint Work, Accepted

A Link Removal Methodology for Network-on-Chip on Reconfigurable Systems

Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

International Conference on Field Programmable Logic and Applications (FPL'08) 269 - 274 2008.09

Research paper (international conference proceedings), Joint Work, Accepted

A Lightweight Fault-tolerant Mechanism for Network-on-chip

Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy M. Pinkston

ACM/IEEE International Symposium on Networks-on-Chip (NOCS'08) 13 - 22 2008.05

Research paper (international conference proceedings), Joint Work, Accepted

Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks

Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano

ACM/IEEE International Symposium on Networks-on-Chip (NOCS'08) 23 - 32 2008.05

Research paper (international conference proceedings), Joint Work, Accepted

Run-Time Power Gating of On-Chip Routers Using Look-Ahead Routing

Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano

Asia and South Pacific Design Automation Conference (ASP-DAC'08) 55 - 60 2008.01

Research paper (international conference proceedings), Joint Work, Accepted

Tightly-Coupled Multi-Layer Topologies for 3-D NoCs

Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

International Conference on Parallel Processing (ICPP'07) 1 - 10 2007.09

Research paper (international conference proceedings), Joint Work, Accepted

A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems

Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

International Conference on Field Programmable Logic and Applications (FPL'07) 383 - 388 2007.08

Research paper (international conference proceedings), Joint Work, Accepted

Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network

Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

IEEE International Parallel and Distributed Processing Symposium (IPDPS'07) 1 - 10 2007.05

Research paper (international conference proceedings), Joint Work, Accepted

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