論文 - 武藤　佳恭

Conjunctoids

Jannarone Robert J., Yu Kai F., Takefuji Yoshiyasu

Neural Networks 1 （ 4 ） 325 - 337 1988年

ISSN  0893-6080

　概要を見る

<p>A general family of fast and efficient neural network learning modules for binary events is introduced. The family subsumes probabilistic as well as functional event associations; subsumes all levels of input/output association; yields truly parallel learning processes; provides for optimal parameter estimation; points toward a workable description of optimal model performance; and yields procedures that are simple and fast enough to be serious candidates for reflecting both neural functioning and real time machine learning. Examples as well as operational details are provided.</p>

• Access to Document (DOI)

ERROR CORRECTING SYSTEM BASED ON NEURAL CIRCUITS.

Takefuji Yoshiyasu, Hollis Paul, Foo Yoon Pin, Cho Yong B.

1987年

　概要を見る

<p>An error-correcting system based on neural circuit techniques is presented. This system is expected to perform significantly faster than conventional error-correcting systems based on logic gate designs. Two example circuits demonstrate how the neural error-correcting system works.</p>

NEURAL NETWORK SCHEME FOR 3-DIMENSIONAL PATTERN RECOGNITION AND CONSTRUCTION.

Foo Yoon Pin Simon, Takefuji Yoshiyasu

1987年

　概要を見る

<p>A neural-based scheme for pattern recognition and construction of three-dimensional images from partial cues is presented. Clusters of neural nets operating concurrently are used to learn and recall patterns at X, Y, Z planes. Simulations are performed based on a Hopfield-like network to investigate the effect of learning trials and firing percentage of nodes per cycle. A method for computing the common features of input patterns is given. Results showed that maximum parallel processing can be achieved.</p>

NEW MODEL OF NEURAL NETWORKS FOR ERROR CORRECTION.

Lii Dzung ji, Takefuji Yoshiyasu

  1709 - 1710 1987年

　概要を見る

<p>A simple example of (7,4) codes for one-bit error correction is shown. However the proposed neural model can be expanded to multiple-bit error correction. Generally an (N,K) neural decoder of this type will require 2**k op amps, an N multiplied by 2**k resistor network, 2**k comparators, and an N multiplied by 2**k diode network. This error-correction model is effective in a severe environment such as control or military equipment's.</p>

AI BASED GENERAL PURPOSE CROSS ASSEMBLER.

Takefuji Yoshiyasu

  75 - 80 1985年

　概要を見る

<p>A general-purpose cross assembler named gpca using Franz Lisp on a VAX11/750 with Berkeley Unix BSD4. 2 was developed. All the user has to do is to provide rule lists to a rule-database for code generation. The rule-based technique used in the gpca can enhance the productivity for developing cross assemblers for 4-, 8-, 16-, and 32-bit microprocessors in a short period of time through the rule independency. The implemented cross-assembler is composed of database management routines, lexical pattern matching routines, and a few other routines. The cross assembler, which is small enough to be understood completely by the user, has a flexibility and an expandability in terms of user extensible pseudo-operations and macro functions.</p>

VLSI SPANNING TREE GENERATORS.

Takefuji Yoshiyasu, Brunson David

  401 - 405 1984年

　概要を見る

<p>Authors propose parallel/pipelined and parallel/iterative spanning tree generators for directed and undirected graphs based on graph theory algorithms using adjacency matrices. A generator employing iterative logic circuits with high regularity suitable for VLSI implementation can be realized with O(n**2) gates where n is the number of nodes in a given graph. This generator can compute a spanning tree of an nXn adjacency matrix within O(n**2) gate delays. The organizations of spanning tree generators are discussed.</p>

FAST MATRIX SOLVER IN GF(2).

Takefuji Yoshiyasu, Kurokawa Takakazu, Aiso Hideo

  138 - 143 1983年

TMR METHOD FOR IMPROVING YIELD OF LARGE MEMORY CHIPS.

Takefuji Yoshiyasu, Adachi Yoshihiko, Aiso Hideo

Systems, computers, controls 13 （ 1 ） 47 - 53 1982年01月

ISSN  0096-8765

　概要を見る

<p>The yield of chips tends to decrease with the degree of integration of memory chips, which is presently a serious problem. A method is proposed to utilize the fault chips being discarded to produce a normal chip, increasing the apparent yield. The relation between the yield and the reliability of the fault memory chip system is discussed. Using the proposed method, the yield of 10% can be improved up to 40% without substantially decreasing the reliability of the fault chip memory system from that of a normal memory chip. The method was implemented using fault 16 K RAM, and the effectiveness of the method was verified.</p>

NOVEL APPROACH TO FAULT-TOLERANT SEQUENTIAL CIRCUITS.

Takefuji Yoshiyasu, Adachi Yoshihiko, Aiso Hideo

  206 - 209 1982年

NOVEL APPROACH TO FAULT-TOLERANT LOGIC AND YIELD ENHANCEMENT.

Takefuji Yoshiyasu, Adachi Yoshihiko, Aiso Hideo

  56 - 64 1982年

NOVEL APPROACH TO FAULT-TOLERANT LOGIC.

Takefuji Yoshiyasu, Ikeda Masahiro

Journal of Information Processing 3 （ 3 ） 119 - 126 1980年

ISSN  0387-6101

　概要を見る

<p>This paper presents a design scheme that supplies logic circuits with very high reliability by providing redundancy to gate function logic using conventional gates. The basic redundant logic circuits are called Fault-Tolerant Gates (FTGs). The construction and design of FTGs, such as AND, OR, NOT, NAND, NOR and Exclusive OR gates, are described. The improved reliability of these FTGs is evaluated in comparison with conventional gates.</p>