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Evaluation of Performance and Power Consumption on Supercomputer Fugaku Using SPEC HPC Benchmarks

Kodama Y., Kondo M., Sato M.

IEICE Transactions on Electronics （IEICE Transactions on Electronics） E106.C （ 6 ） 303 - 311 2023年06月

ISSN 09168524

The supercomputer, “Fugaku”, which ranked number one in multiple supercomputing lists, including the Top500 in June 2020, has various power control features, such as (1) an eco mode that utilizes only one of two floating-point pipelines while decreasing the power supply to the chip; (2) a boost mode that increases clock frequency; and (3) a core retention feature that turns unused cores to the low-power state. By orchestrating these power-performance features while considering the characteristics of running applications, we can potentially gain even better system-level energy efficiency. In this paper, we report on the performance and power consumption of Fugaku using SPEC HPC benchmarks. Consequently, we confirmed that it is possible to reduce the energy by about 17% while improving the performance by about 2% from the normal mode by combining boost mode and eco mode.

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An Interactive and Reductive Graph Processing Library for Edge Computing in Smart Society

Zhou J., Kondo M.

IEICE Transactions on Information and Systems （IEICE Transactions on Information and Systems） E106D （ 3 ） 319 - 327 2023年03月

ISSN 09168532

Due to the limitations of cloud computing on latency, bandwidth and data confidentiality, edge computing has emerged as a novel location-aware paradigm to provide them with more processing capacity to improve the computing performance and quality of service (QoS) in several typical domains of human activity in smart society, such as social networks, medical diagnosis, telecommunications, recommendation systems, internal threat detection, transports, Internet of Things (IoT), etc. These application domains often handle a vast collection of entities with various relationships, which can be naturally represented by the graph data structure. Graph processing is a powerful tool to model and optimize complex problems in which the graph-based data is involved. In view of the relatively insufficient resource provisioning of the portable terminals, in this paper, for the first time to our knowledge, we propose an interactive and reductive graph processing library (GPL) for edge computing in smart society at low overhead. Experimental evaluation is conducted to indicate that the proposed GPL is more user-friendly and highly competitive compared with other established systems, such as igraph, NetworKit and NetworkX, based on different graph datasets over a variety of popular algorithms.

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Exploiting Data Parallelism in Graph-Based Simultaneous Localization and Mapping: A Case Study with GPU Accelerations

Zheng J., He Y., Kondo M.

ACM International Conference Proceeding Series （ACM International Conference Proceeding Series） 126 - 139 2023年02月

Graph-based simultaneous localization and mapping (G-SLAM) is an intuitive SLAM implementation where graphs are used to represent poses, landmarks and sensor measurements when a mobile robot builds a map of the environment and locates itself in it. Being a very important application employed in many realistic scenarios, estimating the whole environment and all trajectories through solving graph problems for SLAM can incur a large amount of computation and consume a significant amount of energy. For the purpose of improving both performance and energy efficiency, we have unveiled the critical path of the G-SLAM algorithm in this paper and implemented a GPU-based solution to aid it. Furthermore, we have attempted to offload performance-critical components (such as matrix inversions when updating the trajectory) in the G-SLAM process into GPUs through CUDA to exploit data parallelism. With our solution, we observe a speed-up of up to 19.7x and an energy saving of up to 83.7% over a modern workstation class x86 CPU; while on a platform dedicated for edge computing (NVIDIA Jetson Nano), we achieve a speed-up of up to 2.5x and an energy saving of up to 6.4% with its integrated GPU, respectively.

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A Scalable Body Bias Optimization Method Toward Low-Power CGRAs

Kojima T., Okuhara H., Kondo M., Amano H.

IEEE Micro （IEEE Micro） 43 （ 1 ） 49 - 57 2023年01月

ISSN 02721732

Body biasing is one of the critical techniques to realize more energy-efficient computing with reconfigurable devices, such as coarse-grained reconfigurable architectures. Its benefit depends on the control granularity, whereas fine-grained control makes it challenging to find the best body bias voltage for each domain due to the complexity of the optimization problem. This work reformulates the optimization problem and introduces continuous relaxation to solve it faster than previous work based on an integer linear program. Experimental result shows the proposed method can solve the problem within 0.5 s for all benchmarks in any conditions. For a middle-class problem, up to 5.65- speedup and a geometric mean of 2.06 - speedup are demonstrated compared to the previous method with negligible loss of accuracy. Besides, we explore finer body bias control considering the power- and area-overhead of an on-chip body bias generator and suggest the most reasonable design saves 66% of energy consumption.

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An Edge-Cloud Collaboration Framework for Graph Processing in Smart Society

Zhou J., Kondo M.

IEEE Transactions on Emerging Topics in Computing （IEEE Transactions on Emerging Topics in Computing） 2023年

Due to the limitations of cloud computing on latency, bandwidth and data confidentiality, edge computing has emerged as a novel location-aware way to provide the capacity-constrained portable terminals with more processing capacity to improve the computing performance and quality of service (QoS) in several typical domains of the human activity in smart society, such as social networks, medical diagnosis, telecommunications, recommendation systems, internal threat detection, transportation, Internet of Things (IoT), etc. These application domains often manage a vast collection of entities with various relationships, which can be naturally represented by the graph data structure. Graph processing is a powerful tool to model and optimize complex problems where graph-based data is involved. In consideration of the relatively insufficient resource provisioning of the edge devices, in this paper, for the first time to our knowledge, we propose a reliable edge-cloud collaboration framework that facilitates the graph primitives based on a lightweight interactive graph processing library (GPL), especially for shortest path search (SPS) operations as the demonstrative example. Two types of different practical cases are also presented to show the typical application scenarios of our graph processing strategy. Experimental evaluations indicate that the acceleration rate of performance can reach 6.87x via graph reduction, and less than 3% and 20% extra latency is required for much better user experiences for navigation and pandemic control, respectively, while the online security measures merely consume about 1% extra time of the overall data transmission. Our framework can efficiently execute the applications with considering of user-friendliness, low-latency response, interactions among edge devices, collaboration between edge and cloud, and privacy protection at an acceptable overhead.

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Memory Bandwidth Conservation for SpMV Kernels Through Adaptive Lossy Data Compression

Hu S., Ito M., Yoshikawa T., He Y., Kondo M.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) （Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)） 13798 LNCS 467 - 480 2023年

ISSN 03029743

SpMV is a very common algorithm in linear algebra, which is widely adopted by machine learning applications nowadays. Especially, fully-connected MLP layers dominate many SpMV tasks that play a critical role in diverse services, and therefore a large fraction of data center cycles are spent. Despite exploiting sparse matrix storage techniques such as CSR/CSC, SpMV still suffers from limited memory bandwidth during data transferring because of the architecture of modern computing systems. However, we find that both integer type and floating-point type data used in matrix-vector multiplications are handled plainly without any necessary pre-processing. We added compression and decompression pre-processing between the main memory and Last Level Cache (LLC) which may dramatically reduce the memory bandwidth consumption. Furthermore, we also observed that convergence speed in some typical scientific computation benchmarks will not be degraded when adopting compressed floating-point data instead of the original double type. Based on these discoveries, in this paper, we propose a simple yet effective compression approach that can be implemented in general computing architectures and HPC systems preferably. When adopting this technique, a performance improvement of 1.92x is made in the best case.

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Multi-Objective Resource Scheduling for IoT Systems Using Reinforcement Learning †

Shresthamali S., Kondo M., Nakamura H.

Journal of Low Power Electronics and Applications （Journal of Low Power Electronics and Applications） 12 （ 4 ） 2022年12月

IoT embedded systems have multiple objectives that need to be maximized simultaneously. These objectives conflict with each other due to limited resources and tradeoffs that need to be made. This requires multi-objective optimization (MOO) and multiple Pareto-optimal solutions are possible. In such a case, tradeoffs are made w.r.t. a user-defined preference. This work presents a general Multi-objective Reinforcement Learning (MORL) framework for MOO of IoT embedded systems. This framework comprises a general Multi-objective Markov Decision Process (MOMDP) formulation and two novel low-compute MORL algorithms. The algorithms learn policies to tradeoff between multiple objectives using a single preference parameter. We take the energy scheduling problem in general Energy Harvesting Wireless Sensor Nodes (EHWSNs) as a case example in which a sensor node is required to maximize its sensing rate, and transmission performance as well as ensure long-term uninterrupted operation within a very tight energy budget. We simulate single-task and dual-task EHWSN systems to evaluate our framework. The results demonstrate that our MORL algorithms can learn better policies at lower learning costs and successfully tradeoff between multiple objectives at runtime.

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Enabling circuit-switching in modern on-chip networks

Jiao J., He Y., Cao T., Kondo M.

Microprocessors and Microsystems （Microprocessors and Microsystems） 95 2022年11月

ISSN 01419331

Contemporary flow control mechanisms, especially virtual channels, are employed by modern on-chip networks to allow better utilization of the link bandwidth through buffering and packet switching. Despite of being the de facto option in designs, they are also the sources of large energy footprint and long per-hop latency. On the other hand, dated and simpler flow controls such as circuit switching can draw far less power while offering an end-to-end latency analogous to wire delay. In this paper, we therefore take a further step from utilizing a single flow control mechanism within the network to allowing circuit-switching to work alongside virtual channels, which provides latency-competitive and energy-efficient on-chip network designs. Furthermore, to enable circuit switching in modern networks-on-chip, we present two independent proposals so that circuits can be formed in a network either temporally or spatially. In our evaluations, we find that both of our proposals can help achieve a very competitive latency per flit, for up to 30% lower with the temporal approach and for up to 10% lower with the spatial approach, while also dramatically suppressing the energy footprint with either approach by up to 27% and 25%, respectively.

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Hash Distributed A∗on an FPGA

Sakamoto R., Ezaki Y., Kondo M.

ACM International Conference Proceeding Series （ACM International Conference Proceeding Series） 76 - 83 2022年06月

Shortest path problem is a problem of finding a path that minimizes the cost of connecting two nodes in a weighted graph. A∗algorithm for solving shortest path search has been applied in various fields such as path navigation systems, automatic robot planning and VLSI design. However, in recent years, the scale of graphs has become large. We need to solve the problem faster and with less power consumption. In this study, we propose a hardware accelerator for solving the shortest path problem using A∗algorithm based on HDA∗(Hash Distributed A∗) using FPGA. In evaluation we compare execution time and power consumption between CPU, GPU and FPGA. FPGA was able to solve Maze problem using the least amount of power. The energy efficiency of FPGA was up to 9 times higher than that of CPU.

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Body Bias Control on a CGRA based on Convex Optimization

Kojima T., Okuhara H., Kondo M., Amano H.

25th IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2022 - Proceedings （25th IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2022 - Proceedings） 2022年

Body biasing is one of the critical techniques to realize more energy-efficient computing with reconfigurable devices, such as Coarse-Grained Reconfigurable Architectures (CGRAs). Its benefit depends on the control granularity, whereas fine-grained control makes it challenging to find the best body bias voltage for each domain due to the complexity of the optimization problem. This work reformulates the optimization problem and introduces continuous relaxation to solve it faster than previous work. Experimental result shows the proposed method can solve the problem within 0.5 sec for all benchmarks in any conditions and demonstrates up to 5.65x speed-up compared to the previous method with negligible loss of accuracy.

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FAWS: Fault-Aware Weight Scheduler for DNN Computations in Heterogeneous and Faulty Hardware

Shresthamali S., He Y., Kondo M.

Proceedings - 20th IEEE International Symposium on Parallel and Distributed Processing with Applications, 12th IEEE International Conference on Big Data and Cloud Computing, 12th IEEE International Conference on Sustainable Computing and Communications and 15th IEEE International Conference on Social Computing and Networking, ISPA/BDCloud/SocialCom/SustainCom 2022 （Proceedings - 20th IEEE International Symposium on Parallel and Distributed Processing with Applications, 12th IEEE International Conference on Big Data and Cloud Computing, 12th IEEE International Conference on Sustainable Computing and Communications and 15th IEEE International Conference on Social Computing and Networking, ISPA/BDCloud/SocialCom/SustainCom 2022） 204 - 212 2022年

The idea of using inexact computation for overprovisioned DNNs (Deep Neural Networks) to decrease power and la-tency at the cost of minor accuracy degradation has become very popular. However, there is still no general method to schedule DNN computations on a given hardware platform to effectively implement this idea without loss in computational efficiency. Most contemporary methods require specialized hardware, ex-tensive retraining and hardware-specific scheduling schemes. We present FAWS: Fault-Aware Weight Scheduler for scheduling DNN computations in heterogeneous and faulty hardware. Given a trained DNN model and a hardware fault profile, our scheduler is able to recover significant accuracy during inference even at high fault rates. FAWS schedules the computations such that the low priority ones are allocated to inexact hardware. This is achieved by shuffling (exchanging) the rows of the matrices. The best shuffling order for a given DNN model and hardware fault profile is determined using Genetic Algorithms (GA). We simulate bitwise errors on different model architectures and datasets with different types of fault profiles and observe that FAWS can recover up to 30% of classification accuracy even at high fault rates (which correspond to approximately 50 % power savings).

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QULATIS: A Quantum Error Correction Methodology toward Lattice Surgery

Ueno Y., Kondo M., Tanaka M., Suzuki Y., Tabuchi Y.

Proceedings - International Symposium on High-Performance Computer Architecture （Proceedings - International Symposium on High-Performance Computer Architecture） 2022-April 274 - 287 2022年

ISSN 15300897

Due to the high error rate of a qubit, detecting and correcting errors on it is essential for fault-tolerant quantum computing (FTQC). Surface code (SC) associated with its decoding algorithm is one of the most promising quantum error correction (QEC) methods because it has high fidelity and requires only nearest neighbor qubits connectivity. To realize FTQC, we need a decoder circuit capable of not only QEC in a 3-D lattice to deal with errors in measurement on ancillary qubits but also quantum operations on logically constructed qubits. Whereas several methods to perform logical operations on SC, such as lattice surgery (LS), are known, no practical decoders supporting them have been proposed yet.One of the most promising QC implementations today is made up of superconducting qubits that are located in a cryogenic environment. To reduce the hardware complexity of QC and latency of QEC, we are supposed to perform QEC in a cryogenic environment. Hence a power-efficient decoder is required due to the limited power budget inside a dilution refrigerator.In this paper, we propose an online-QEC algorithm that supports LS with a practical decoder circuit, as well as a new FTQC architecture. We design a key building block of the proposed architecture with a hybrid of SFQ- and Cryo-CMOS-based digital circuits and evaluate it with a SPICE-level simulation. Each logic element includes about 2400 Josephson junctions, and power consumption is estimated to be 2.07 μW when operating with a 2 GHz clock frequency. We evaluate the decoder performance by a quantum error simulator for an essential operation of LS with code distances up to 11, and it achieves a 0.6% accuracy threshold. In an LS-based architecture further supporting a magic-state distillation protocol, which is expected to run for near-term universal quantum computing, we evaluate the QEC performance and power consumption of the architecture and show that it is practical to be operated in 4-K temperature region of a dilution refrigerator.

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ONLAD-IDS: ONLAD-Based Intrusion Detection System Using SmartNIC

Wu M., Matsutani H., Kondo M.

Proceedings - 24th IEEE International Conference on High Performance Computing and Communications, 8th IEEE International Conference on Data Science and Systems, 20th IEEE International Conference on Smart City and 8th IEEE International Conference on Dependability in Sensor, Cloud and Big Data Systems and Application, HPCC/DSS/SmartCity/DependSys 2022 （Proceedings - 24th IEEE International Conference on High Performance Computing and Communications, 8th IEEE International Conference on Data Science and Systems, 20th IEEE International Conference on Smart City and 8th IEEE International Conference on Dependability in Sensor, Cloud and Big Data Systems and Application, HPCC/DSS/SmartCity/DependSys 2022） 546 - 553 2022年

Machine learning- or neural network-based intrusion detection systems (IDSs) demonstrate the state-of-the-art performance and confidence in current threat detection. However, due to the increasing sophistication of today's network attacks and the growing cost of obtaining attack labels for network traffic, updating an IDS model with labeled data requires significant effort. Furthermore, in real-time developments of the Internet of Things (IoT), network flow input and large-size deep learning models impose additional latency and low throughput due to the hardware resource, bandwidth, and programming cost. To this end, this paper proposes an on-device sequential learning semi-supervised anomaly detector-based intrusion detection system (ONLAD-IDS) using smart interface network cards (NICs) to address these challenges. The ONLAD- IDS consists of packet sniffing, feature extractor, feature selection with analysis of variance (ANOVA), and an ONLAD model. Moreover, the real-time throughput ONLAD-IDS is developed by the Nvidia Bluefield DPU with smartNICs without programming cost. Experiments show that ONLAD-IDS achieves a throughput of 1486.095 packet/ms and a detection rate of 0.7523 on DPU with a 25Gb/s transmission throughput while maintaining high detection performance.

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Interactive and Reliable Graph Processing via the Edge-Cloud Collaboration Framework

Zhou J., Kondo M.

Due to the limitations of cloud computing on latency, bandwidth and data confidentiality, edge computing has emerged as a novel location-aware paradigm to provide the capacity constrained portable terminals with more processing capacity to improve the performance and quality of service (QoS) in several typical domains of the human activity in smart society, such as social networks, medical diagnosis, transportation, Internet of Things (IoT), etc. These domains often handle a vast collection of entities with various relationships which can be naturally represented by graph data structures. Graph processing is a powerful tool to model and optimize the complex problems where the graph-based data is involved. In view of the relatively insufficient resource provision of the edge devices, for the first time to our knowledge, we propose a reliable edge-cloud collaboration framework facilitating the shortest path search (SPS) operations based on a lightweight interactive graph processing library. One practical case is presented as well to show the typical application scenarios of our graph processing strategy. Experimental evaluation is conducted to indicate that the proposed strategy is able to efficiently implement the relevant application tasks with considering user-friendliness, low-latency response, collaborations between edge and cloud, interactions among edge devices, and privacy protection at an acceptable overhead.

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GraphDEAR: An Accelerator Architecture for Exploiting Cache Locality in Graph Analytics Applications

Hu S., Kondo M., He Y., Sakamoto R., Zhang H., Zhou J., Nakamura H.

Proceedings - 30th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2022 （Proceedings - 30th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2022） 135 - 143 2022年

Data structure is the key in Edge Computing where various types of data are continuously generated by ubiquitous devices. Within all common data structures, graphs are used to express relationships and dependencies among human identities, objects, and locations; and they are expected to become one of the most important data infrastructure in the near future. Furthermore, as graph processing often requires random accesses to vast memory spaces, conventional memory hierarchies with caches cannot perform efficiently. To alleviate such memory access bottlenecks in graph processing, we present a solution through vertex accesses scheduling and edge array re-ordering, in parallel with the execution of graph processing application to improve both temporal and spatial locality of memory accesses, especially for edge-centric graphs which are popular means in handling dynamic graphs. Our proposed architecture is evaluated and tested through both trace-based cache simulations and cycle-Accurate FPGA-based prototyping. Evaluation results show that our proposal has a potential of significantly reducing the quantity of Miss-Per-Kilo-Instructions (MPKI) for Last Level Cache (LLC) by 56.27% on average.

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QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface Code

Ueno Y., Kondo M., Tanaka M., Suzuki Y., Tabuchi Y.

Proceedings - Design Automation Conference （Proceedings - Design Automation Conference） 2021-December 451 - 456 2021年12月

ISSN 0738100X

Due to the low error tolerance of a qubit, detecting and correcting errors on it is essential for fault-tolerant quantum computing. Surface code (SC) associated with its decoding algorithm is one of the most promising quantum error correction (QEC) methods. QEC needs to be very power-efficient since the power budget is limited inside of a dilution refrigerator for superconducting qubits by which one of the most successful quantum computers (QCs) is built. In this paper, we propose an online-QEC algorithm and its hardware implementation with SFQ based superconducting digital circuits. We design a key building block of the proposed hardware with an SFQ cell library and evaluate it by the SPICE-level simulation. Each logic element is composed of about 3000 Josephson junctions and power consumption is about 2.78 μW when operating with 2 GHz clock frequency which meets the required decoding speed. Our decoder is simulated on a quantum error simulator for code distances 5 to 13 and achieves a 1.0% accuracy threshold.

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FPGA-Based Acceleration of FDTD Sound Field Rendering

Tan Y., Imamura T., Kondo M.

AES: Journal of the Audio Engineering Society （AES: Journal of the Audio Engineering Society） 69 （ 7-8 ） 542 - 556 2021年07月

ISSN 15494950

Sound field rendering is computation-intensive and memory-intensive. This research investigates an FPGA-based accelerator for sound field rendering with an FDTD scheme, in which wave equations are directly implemented by reconfigurable hardware, and spatial blocking is applied to alleviate the memory bandwidth requirement. Compared to software simulation performed on a desktop machine with 128 GB DDR4 RAMs and an Intel i7-7820X processor running at 3.6 GHz, the proposed FPGA-based accelerator achieves up to 2.98 times more in computing performance in the case of different layer sizes and different numbers of nodes computed in parallel even though the FPGA system runs at about 267 MHz.

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Federated Learning-Based Network Intrusion Detection with a Feature Selection Approach

Qin Y., Kondo M.

3rd International Conference on Electrical, Communication and Computer Engineering, ICECCE 2021 （3rd International Conference on Electrical, Communication and Computer Engineering, ICECCE 2021） 2021年06月

With the increase and diversity of network attacks, machine learning has shown its efficiency in realizing intrusion detection. Federated Learning (FL) has been proposed as a new distributed machine learning approach, which collaboratively trains a prediction model by aggregating local models of users without sharing their privacy-sensitive data. Recently, the approach is applied to optimize intrusion detection for resourced-constrained environments. However, since the attacks are becoming more sophisticated and targeted, there is also a growing need to enhance detection models according to the characteristics of attack type; meanwhile, choosing effective feature sets from the network traffic characteristics is considered one of the most important technologies in data analysis. In this paper, we first proposed a federated learning-based intrusion detection system with feature selection technology. Firstly, a greedy algorithm is suggested to select features that achieve better intrusion detection accuracy regarding different attack categories. Afterward, multiple global models are generated by the server in federated learning, according to the decided features of edge devices. For evaluating the effectiveness of the proposed approach, simulation experiments based on the latest on-device neural network for anomaly detection are conducted over the NSL-KDD dataset. Experimental results demonstrate greatly improved accuracy of our method.

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Efficient and precise profiling, modeling and management on power and performance for power constrained hpc systems

HE Y., WADA Y., LUO W., SAKAMOTO R., PAN G., CAO T., KONDO M.

IEICE Transactions on Electronics （IEICE Transactions on Electronics） 1 （ 6 ） 237 - 246 2021年06月

ISSN 09168524

Due to the slowdown of Moore's Law, power limitation has been one of the most critical issues for current and future HPC systems. To more efficiently utilize HPC systems when power budgets or deadlines are given, it is very desirable to accurately estimate the performance or power consumption of applications before conducting their tuned production runs on any specific systems. In order to ease such estimations, we showcase a straight-forward and yet effective method, based on the enhanced power management framework and DSL we developed, to help HPC users to clarify the performance and power relationships of their applications. This method demonstrates an easy process of profiling, modeling and management on both performance and power of HPC systems and applications. In our evaluations, only a few (up to 3) profiled runs are necessary before very precise models of HPC applications can be obtained through this method (and algorithm), which has dramatically improved the efficiency of and lowered the difficulty in utilizing HPC systems under limited power budgets.

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Density-Based Data Selection and Management for Edge Computing

Oikawa H., Kondo M.

2021 IEEE International Conference on Pervasive Computing and Communications, PerCom 2021 （2021 IEEE International Conference on Pervasive Computing and Communications, PerCom 2021） 2021年03月

Wide spread of IoT devices has made it possible to acquire enormous amounts of realtime sensor information. Due to the explosive increase in the sensing data volume, it becomes difficult to collect and process all the data in one central place. On one hand, storing and processing data on edge devices, so called edge computing, is becoming important. On the other hand, edge devices usually have only limited computing and memory resources, and hence it is not practical to process and save all the acquired data. There is a great demand of effectively selecting data to process on an edge device or to transfer it to a cloud server. In this paper, we propose an efficient density-based data selection and management method called O-D2M by which edge devices store the data representing inherent data distribution. We use a low cost graph algorithm to analyze input data trend and its density. We evaluate effectiveness of the proposed O-D2M comparing to other methods in terms of the accuracy of machine learning models trained by the selected data. Throughout the evaluation, we confirm that O-D2M obtains higher accuracy and lower computation cost while it can reduce the amount of data to be processed or transferred by up to 20 points.

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MLMG: Multi-Local and Multi-Global Model Aggregation for Federated Learning

Qin Y., Kondo M.

2021 IEEE International Conference on Pervasive Computing and Communications Workshops and other Affiliated Events, PerCom Workshops 2021 （2021 IEEE International Conference on Pervasive Computing and Communications Workshops and other Affiliated Events, PerCom Workshops 2021） 565 - 571 2021年03月

Federated learning has attracted much interest and attention as a solution to collaboratively learn a prediction model without sharing the training data of users. Existing federated learning approaches usually develop a single independent local model for each client to train their privacy-sensitive data, afterward adopt a single centralized global model to exchange the trained parameters of clients that participate in federated training. However, given the diverse characteristics of local data and the heterogeneity across participating clients, the conventional federated learning paradigm may not achieve uniformly good performance over all users. In this work, we propose a novel federated learning mechanism which suggests using a Multi-Local and Multi-Global (MLMG) model aggregation to train the non-IID user data with clustering methods. Then a Matching algorithm is introduced to derive the appropriate exchanges between local models and global models. The new federated learning mechanism helps separate the data and user with different characteristics, thus makes it easier to capture the heterogeneity of data distributions across the users. We choose the latest on-device neural network for anomaly detection to evaluate the proposal, and experimental results based on several benchmark datasets demonstrate better detection accuracy (up to 2.83% accuracy improvement) of the novel paradigm compared with a conventional federated learning approach.

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Path planning and moving obstacle avoidance with neuromorphic computing

Sakurai M., Ueno Y., Kondo M.

ISR 2021 - 2021 IEEE International Conference on Intelligence and Safety for Robotics （ISR 2021 - 2021 IEEE International Conference on Intelligence and Safety for Robotics） 209 - 215 2021年03月

Neuromorphic computing has been getting attention because of its potential for fast and low-power computation, robustness, and learning capability. Though traditional machine learning applications are main target of neuromorphic computing, its characteristic of parallel and distributed processing with simple spike-based signals is useful for other types of applications such as a shortest path finding problem (SPFP) on a graph. Prior work discussed approaches for mapping SPFP to a spiking neural network (SNN). In this paper, we propose an SNN algorithm for path planning with moving obstacles. In real world situation, there are many moving obstacles (such as other cars for an autonomous driving car and human for a moving robot) around a target agent which tries to optimize its own path to the goal. Finding an effective path in such an environment is not an easy task since behavior of obstacles is sometimes unknown and there must be a huge number of candidate paths to go. Traditional methods for SPFP with a general CPU may not be effective since it should compare candidate paths and select the most suitable one every time step. We consider two agents with SNN which tries to achieve two goals: 'reaching its destination promptly' and 'avoiding moving obstacles properly'. Thanks to SNN properties, the agent can learn and estimate how the obstacles move. We compare the proposal approaches with an existing method on a 2D grid graph and the result shows that the proposal agents can select proper paths depending on obstacles' movement.

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Local Traffic-Based Energy-Efficient Hybrid Switching for On-Chip Networks

He Y., Jiao J., Kondo M.

Proceedings - 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2021 （Proceedings - 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2021） 198 - 206 2021年03月

Advanced flow control mechanisms employed by modern on-chip networks are the reasons of large energy footprint and long per-hop latency. On the other hand, dated and simpler flow controls such as circuit switching can draw far less power and offer an end-to-end latency analogous to wire delay. In this paper, we present a hybrid flow control mechanism, which mixes both virtual channels and circuit-switching, to provide a latency-competitive and energy-efficient on-chip network design. Contrary to existing hybrid switching designs, our proposal is based on local traffic so that circuits are formed without the knowledge of end-to-end traffic. When compared to on-chip networks with virtual channels, our proposal achieves a very competitive latency per flit, for up to 4% lower, while also dramatically suppressing the energy per flit by up to 18%.

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A Lightweight Interactive Graph Processing Library for Edge Computing in Smart Society

Zhou J., Kondo M.

Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021 （Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021） 62 - 68 2021年

Edge computing aims to handle the data very close to the source where it is produced, and also provides an effective way to alleviate the burden of cloud computing for the processing of massive volume of data, enabling lower latency, faster response, and more comprehensive data analyses. Meanwhile, graph-based data has emerged especially in the form of social networks, World Wide Web (WWW), transportation, biological networks, and so on, which become high-impact domains of human activity to build smart society. Generally, as the resources on compact end devices are strictly constrained, a graph processing solution with low latency and low overhead is a real necessity for graph analytics in edge computing. In this paper, for the first time to our knowledge, we propose a lightweight interactive graph processing library (GPL) for edge computing in smart society, which is user-friendly and handy to be operated on a single device or among multiple devices. Evaluation is conducted to indicate that the proposed GPL is highly competitive with other established libraries such as igraph, NetworKit or NetworkX based on different graph datasets over a variety of popular algorithms.

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Evaluation of SPEC CPU and SPEC OMP on the A64FX

Kodama Y., Kondo M., Sato M.

Proceedings - IEEE International Conference on Cluster Computing, ICCC （Proceedings - IEEE International Conference on Cluster Computing, ICCC） 2021-September 553 - 561 2021年

ISSN 15525244

We evaluated the A64FX processor used in the supercomputer Fugaku using the SPEC CPU and SPEC OMP benchmark suites. As a result, we found the performance of the A64FX processor, which had 48 cores, was lower than that of the Xeon with dual sockets of 24 cores each in SPEC CPU int and fp. In SPEC OMP, due to the effect of the Xeon's Hyperthread, the A64FX performance was lower than the performance of the Xeon with single socket of 28 cores. But in several benchmarks in SPEC CPU fp and SPEC OMP, the A64FX performance was higher due to its high memory bandwidth. In addition, by comparing the performance and power using the power control mechanism of the A64FX, it was confirmed that power can be reduced without affecting the performance when not using all cores.

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Multi-objective Reinforcement Learning for Energy Harvesting Wireless Sensor Nodes

Shresthamali S., Kondo M., Nakamura H.

Proceedings - 2021 IEEE 14th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2021 （Proceedings - 2021 IEEE 14th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2021） 98 - 105 2021年

Modern Energy Harvesting Wireless Sensor Nodes (EHWSNs) need to intelligently allocate their limited and unreliable energy budget among multiple tasks to ensure long-term uninterrupted operation. Traditional solutions are ill-equipped to deal with multiple objectives and execute a posteriori tradeoffs. We propose a general Multi-objective Reinforcement Learning (MORL) framework for Energy Neutral Operation (ENO) of EHWSNs. Our proposed framework consists of a novel Multi-objective Markov Decision Process (MOMDP) formulation and two novel MORL algorithms. Using our framework, EHWSNs can learn policies to maximize multiple task-objectives and perform dynamic runtime tradeoffs. The high computation and learning costs, usually associated with powerful MORL algorithms, can be avoided by using our comparatively less resource-intensive MORL algorithms. We evaluate our framework on a general single-task and dual-task EHWSN system model through simulations and show that our MORL algorithms can successfully tradeoff between multiple objectives at runtime.

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Mitigating Process Variations with Cooperative Tuning for Performance and Power through a Simple DSL

Ma Y., He Y., Wada Y., Luo W., Sakamoto R., Kondo M.

As the feature size of transistors continues to scale down, process variations have been a critical issue for large scale computer systems, such as high-performance or warehouse-scale computers, to realize energy efficient operations. With process variations, it is very hard to effectively utilize the given power budget for such systems as many components inside them simply draw different amount of power for the same performance, even if they have the same hardware specifications. To allow such computer systems to operate in an accurate and energy-efficient manner, we demonstrate how calibrations, modelling and load balancing are realized to address process variations with an simple in-house DSL. With our case studies and evaluations, we prove the effectiveness of our tools and approaches as the impacts from process variations in our experimental system is minimized with considerably smaller amount of effort, which leads to highly energy efficient executions of parallel applications and dramatic reductions in profiling overheads.

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A Selective Model Aggregation Approach in Federated Learning for Online Anomaly Detection

Qin Y., Matsutani H., Kondo M.

Proceedings - IEEE Congress on Cybermatics: 2020 IEEE International Conferences on Internet of Things, iThings 2020, IEEE Green Computing and Communications, GreenCom 2020, IEEE Cyber, Physical and Social Computing, CPSCom 2020 and IEEE Smart Data, SmartData 2020 （Proceedings - IEEE Congress on Cybermatics: 2020 IEEE International Conferences on Internet of Things, iThings 2020, IEEE Green Computing and Communications, GreenCom 2020, IEEE Cyber, Physical and Social Computing, CPSCom 2020 and IEEE Smart Data, SmartData 2020） 684 - 691 2020年11月

ISSN 9781728176475

Cloud computing has established a convenient approach for computing offloading, where the data produced by edge devices is gathered and processed in a centralized server. However, it results in critical issues related to latency. Recently, a neural network-based on-device learning approach is proposed, which offers a solution to the latency problem by relocating processing data to edge devices; even so, a single edge device may face insufficient training data to train a high-quality model, because of its limited available processing capabilities and energy resources. To address this issue, we extend the work to a federated learning system which enables the edge devices to exchange their trained parameters and update local models. However, in federated learning for anomaly detection, the reliability of local models would be different. For example, a number of trained models are likely to contain the features of anomalous data because of noise corruption or anomaly detection failure. Besides, as the communication protocol amongst edges could be exploited by attackers, the training data or model weights may have potential risks of being poisoned. Therefore, when we design a federated training algorithm, we should carefully select the local models that participate in model aggregation. In this work, we leverage an observed dataset to compute prediction errors, so that the unsatisfying local models can be excluded from federated training. Experimental results show that the federated learning approach improves anomaly detection accuracy. Besides, the proposed model aggregation solution achieves obvious improvement compared with the popular Federated Averaging method.

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Fast Semi-Supervised Anomaly Detection of Drivers' Behavior using Online Sequential Extreme Learning Machine

Oikawa H., Nishida T., Sakamoto R., Matsutani H., Kondo M.

2020 IEEE 23rd International Conference on Intelligent Transportation Systems, ITSC 2020 （2020 IEEE 23rd International Conference on Intelligent Transportation Systems, ITSC 2020） 2020年09月

ISSN 9781728141497

With the wide spread of artificial intelligence (AI) technologies, many applications using AI are increasingly deployed in many fields. Specially anomaly detection is one of the key applications of AI. Among several targets, detecting anomaly behavior of drivers or vehicles has been attracting due to the growing demand of safety driving. It is crucial to study and evaluate techniques for anomaly driving detection with AI technologies. The Online Sequential Extreme Learning Machine (OS-ELM) is a recently attracting neural network model that has high memory efficiency and can perform highspeed sequential learning with streaming data. Though OSELM is known to be effective for anomaly detection, it has not yet been verified for non-stationary time series data such as driving sensor data. In this paper, we study the effectiveness of OS-ELM based anomaly driving behavior detector using sensor data of vehicles and compared the performance of it with a Hidden Markov Model (HMM) based and traditional Long Short-Term Memory (LSTM) based methods. Since the existing driving behavior benchmark data is not enough for evaluating anomaly driving, we also create a new dataset with a powered wheelchair. Throughout the evaluation, we show that the OS-ELM based anomaly driving detector has almost the same or even better accuracy in anomaly driving detection with much faster sequential learning speed compared with the HMM or LSTM based detector.

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Energy-efficient on-chip networks through profiled hybrid switching

He Y., Jiao J., Cao T., Kondo M.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI （Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI） 241 - 246 2020年09月

ISSN 9781450379441

Virtual channel (VC) flow control is the de facto choice for modern networks-on-chip (NoCs) to allow better utilization of the link bandwidth through buffering and packet switching (PS), which are also the sources of large power footprint and long per-hop latency. However, bandwidth can be plentiful for parallel workloads under VC flow control. Thus, dated but simpler mechanisms, such as circuit switching (CS), can help improve the energy efficiency of modern NoCs. In this paper, we propose to apply CS to part of the link bandwidth so that a considerable amount of traffic can be transmitted bufferlessly without routing. Evaluations reveal that this proposal leads to a reduction of energy per flit by up to 32% while also provides very competitive latency when compared to networks under VC flow control.

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A neural network-based on-device learning anomaly detector for edge devices

Tsukada M., Kondo M., Matsutani H.

IEEE Transactions on Computers （IEEE Transactions on Computers） 69 （ 7 ） 1027 - 1044 2020年07月

ISSN 00189340

Semi-supervised anomaly detection is an approach to identify anomalies by learning the distribution of normal data. Backpropagation neural networks (i.e., BP-NNs) based approaches have recently drawn attention because of their good generalization capability. In a typical situation, BP-NN-based models are iteratively optimized in server machines with input data gathered from the edge devices. However, (1) the iterative optimization often requires significant efforts to follow changes in the distribution of normal data (i.e., concept drift), and (2) data transfers between edge and server impose additional latency and energy consumption. To address these issues, we propose ONLAD and its IP core, named ONLAD Core. ONLAD is highly optimized to perform fast sequential learning to follow concept drift in less than one millisecond. ONLAD Core realizes on-device learning for edge devices at low power consumption, which realizes standalone execution where data transfers between edge and server are not required. Experiments show that ONLAD has favorable anomaly detection capability in an environment that simulates concept drift. Evaluations of ONLAD Core confirm that the training latency is 1.95x∼6.58x faster than the other software implementations. Also, the runtime power consumption of ONLAD Core implemented on PYNQ-Z1 board, a small FPGA/CPU SoC platform, is 5.0x∼25.4x lower than them.

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The Effectiveness of Low-Precision Floating Arithmetic on Numerical Codes: A Case Study on Power Consumption

Sakamoto R., Kondo M., Fujita K., Ichimura T., Nakajima K.

ACM International Conference Proceeding Series （ACM International Conference Proceeding Series） 199 - 206 2020年01月

ISSN 9781450372367

The low-precision floating point arithmetic that performs computation by reducing numerical accuracy with narrow bit-width is attracting since it can improve the performance of the numerical programs. Small memory footprint, faster computing speed, and energy saving are expected by performing calculation with low precision data. However, there have not been many studies on how low-precision arithmetics affects power and energy consumption of numerical codes. In this study, we investigate the power efficiency improvement by aggressively using low-precision arithmetics for HPC applications. In our evaluations, we analyze power characteristics of the Poisson's equation and the ground motion simulation programs with double precision and single precision floating point arithmetics. We confirm that energy efficiency improves by using low-precision arithmetics but it is heavily influenced by parameters such as data division and the number of OpenMP threads.

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Power management of wireless sensor nodes with coordinated distributed reinforcement learning

Shresthamali S., Kondo M., Nakamura H.

Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019 （Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019） 638 - 647 2019年11月

ISSN 9781538666487

Energy Harvesting Wireless Sensor Nodes (EHWSNs) require adaptive energy management policies for uninterrupted perpetual operation in their physical environments. Contemporary online Reinforcement Learning (RL) solutions take an unrealistically long time exploring the environment to converge on working policies. Our work accelerates learning by partitioning the state-space for simultaneous exploration by multiple agents. We achieve this by using a novel coordinated e-greedy method and implement it via Distributed RL (DiRL) in an EHWSN network. Our simulation results show a four-fold increase in state-space penetration and reduction in time to achieve optimal operation by an order of magnitude (50x). Moreover, we also propose methods to reduce instances of disastrous outcomes associated with learning and exploration. This translates to reducing the downtimes of the nodes in simulations corresponding to a real-world scenario by one thirds.

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A Preliminary evaluation of building block computing systems

Terashima S., Kojima T., Okuhara H., Musha K., Amano H., Sakamoto R., Kondo M., Namiki M.

Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019 （Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019） 312 - 319 2019年10月

ISSN 9781728148823

A building block computing system with inductive coupling Through Chip Interface (TCI) consists of 3-D chip stack, each of which is small dedicated chips. By changing the combination of stacked chips, various types of systems can be built. A MIPS R3000 compatible processor GeyserTT, a neural network accelerator SNACC and the shared memory for building the twin-Tower of chips SMTT have been developed with a Renesas 65nm low leakage CMOS process. They provide the TCI IP (Intellectual Property), and an escalator network is built just by stacking them. This paper shows each chip evaluation results and performance estimation of stacking them with the RTL simulator. The performance of the single-Tower and twin-Tower configuration is estimated by RTL simulation when a part of Alexnet is implemented. The evaluation results showed that the single-Tower configuration with GeyserTT+SNACC achieved about twice performance as the case with GeyserTT. Also, experimental results using each of the single real chip showed that all of them work at least 50MHz with extremely low power consumption. The twin-Tower configuration achieved about 2x of the single-Tower, that is about 6x of GeyserTT. The power consumption was about 276mW for the single-Tower and 496mW for the twin-Tower.

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An adaptive abnormal behavior detection using online sequential learning

Ito R., Tsukada M., Kondo M., Matsutani H.

Proceedings - 22nd IEEE International Conference on Computational Science and Engineering and 17th IEEE International Conference on Embedded and Ubiquitous Computing, CSE/EUC 2019 （Proceedings - 22nd IEEE International Conference on Computational Science and Engineering and 17th IEEE International Conference on Embedded and Ubiquitous Computing, CSE/EUC 2019） 436 - 440 2019年08月

ISSN 9781728116631

In the real world, normal and abnormal behavior patterns vary depending on a given environment, which means that the abnormal behavior detection model should be customized. To address this issue, in this paper, we employ OS-ELM (Online Sequential Extreme Learning Machine) and Autoencoder for adaptive abnormal behavior detection. First, state-transition probability tables of a target during an initial learning period are learned as normal behaviors. Then, Autoencoder-based anomaly detection is performed for the state-transition probability tables of subsequent time frames. The abnormal behavior detection model is updated by using OS-ELM algorithm every time a new probability table or behavior comes. The number of abnormal behavior detection instances is dynamically tuned to reflect the recent normal patterns or modes. Also, the table is compressed to reduce the computation cost. Evaluation results using a driving dataset of cars show that the proposed abnormal behavior detection accurately identifies normal and aggressive driving patterns with the optimal number of the abnormal behavior detection instances.

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OS-ELM-FPGA: An FPGA-based online sequential unsupervised anomaly detector

Tsukada M., Kondo M., Matsutani H.

ISSN 9783030105488

Autoencoder, a neural-network based dimensionality reduction algorithm has demonstrated its effectiveness in anomaly detection. It can detect whether an input sample is normal or abnormal by just training only with normal data. In general, Autoencoder is built on backpropagation-based neural networks (BP-NNs). When BP-NNs are implemented in edge devices, they are typically specialized only for prediction with weight matrices precomputed offline due to the high computational cost. However, such devices cannot be immediately adapted to time-series trend changes of input data. In this paper, we propose an FPGA-based unsupervised anomaly detector, called OS-ELM-FPGA, that combines Autoencoder and an online sequential learning algorithm OS-ELM. Based on our theoretical analysis of the algorithm, the proposed OS-ELM-FPGA completely eliminates matrix pseudoinversions while improving the learning throughput. Simulation results using open-source datasets show that OS-ELM-FPGA achieves favorable anomaly detection accuracy compared to CPU and GPU implementations of BP-NNs. Learning throughput of OS-ELM-FPGA is 3.47x to 27.99x and 5.22x to 78.06x higher than those of CPU and GPU implementations of OS-ELM. It is also 3.62x to 36.15x and 1.53x to 43.44x higher than those of CPU and GPU implementations of BP-NNs.

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Power management framework for post-petascale supercomputers

Kondo M., Miyoshi I., Inoue K., Miwa S.

Advanced Software Technologies for Post-Peta Scale Computing: The Japanese Post-Peta CREST Research Project （Advanced Software Technologies for Post-Peta Scale Computing: The Japanese Post-Peta CREST Research Project） 249 - 269 2018年12月

ISSN 9789811319235

Power consumption is a first class design constraint for developing future exascale computing systems. To achieve exascale system performance with realistic power provisioning of 20-30MW, we need to improve power-performance efficiency significantly compared to today's supercomputer systems. In order to maximize effective performance within a power constraint, investigating how to optimize power resource allocation to each hardware component or each job submitted to the system is necessary. We have been conducting research and development on a software framework for code optimization and system power management for the power-constraint adaptive systems. We briefly introduce the research efforts for maximizing application performance under a given power constraint, power-aware resource manager, and power-performance simulation and analysis framework for future supercomputer systems.

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Analyzing resource trade-offs in hardware overprovisioned supercomputers

Sakamoto R., Patki T., Cao T., Kondo M., Inoue K., Ueda M., Ellsworth D., Rountree B., Schulz M.

Proceedings - 2018 IEEE 32nd International Parallel and Distributed Processing Symposium, IPDPS 2018 （Proceedings - 2018 IEEE 32nd International Parallel and Distributed Processing Symposium, IPDPS 2018） 526 - 535 2018年08月

ISSN 9781538643686

Hardware overprovisioned systems have recently been proposed as a viable alternative for a power-efficient design of next-generation supercomputers. A key challenge for such systems is to determine the degree of overprovisioning, which refers to the number of extra nodes that need to be installed under a given power constraint. In this paper, we first show that the degree of overprovisioning depends on dynamic parameters, such as the job mix as well as the global power constraint, and that static decisions can result in limited system throughput. We then study an exhaustive combination of adaptive resource management strategies that span three job scheduling algorithms, four power capping techniques, and three node boot-up mechanisms to understand the trade-off space involved. We then draw conclusions about how these strategies can adaptively control the degree of overprovisioning and analyze their impact on job throughput and power utilization.

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Building block multi-chip systems using inductive coupling through chip interface

Amano H., Kuroda T., Nakamura H., Usami K., Kondo M., Matsutani H., Namiki M.

Proceedings - International SoC Design Conference 2017, ISOCC 2017 （Proceedings - International SoC Design Conference 2017, ISOCC 2017） 152 - 154 2018年05月

ISSN 9781538622858

A building block computing system is consisting of multiple chips connecting with inductive coupling wireless through chip interconnect. Like building Lego blocks, various types of systems can be built by stacking different types of chips. In order to develop such systems, several techniques are investigated in the project: that is, inductive coupling wireless through chip interface, low power circuit technologies, autonomous interconnection network architectures, thermal dissipation and building block operating system. Here, the overview of the project and a prototype system are introduced.

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Scalable deep neural network accelerator cores with cubic integration using through chip interface

Sakamoto R., Takata R., Ishii J., Kondo M., Nakamura H., Ohkubo T., Kojima T., Amano H.

Proceedings - International SoC Design Conference 2017, ISOCC 2017 （Proceedings - International SoC Design Conference 2017, ISOCC 2017） 155 - 156 2018年05月

ISSN 9781538622858

Due to the recent advances in Deep Neural Network (DNN) technologies, recognition and inference applications are expected to run on mobile embedded systems. Developing high-performance and power-efficient DNN engines becomes one of the important challenges for embedded systems. Since DNN algorithms or structures are frequently updated, flexibility and performance scalability to deal with various types of networks are crucial requirement of the DNN accelerator design. In this paper, we describe the architecture and LSI design of a flexible and scalable CNN accelerator called SNACC (Scalable Neuro Accelerator Core with Cubic integration) which consists of several processing cores, on-chip memory modules, and ThruChip Interface (TCI).

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The design and implementation of scalable deep neural network accelerator cores

Sakamoto R., Takata R., Ishii J., Kondo M., Nakamura H., Ohkubo T., Kojima T., Amano H.

Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017 （Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017） 2018-January 13 - 20 2018年03月

ISSN 9781538634417

Due to the recent advances in Deep Neural Network (DNN) technologies, recognition and inference applications are expected to run on mobile embeddedsystems. Developing high-performance and power-efficient DNN engines becomesone of the important challenges for embedded systems. Since DNN algorithms orstructures are frequently updated, flexibility and performance scalability todeal with various types of networks are crucial requirement of the DNNaccelerator design. In this paper, we describe the architecture and LSI designof a flexible and scalable CNN accelerator called SNACC (Scalable NeuroAccelerator Core with Cubic integration) which consists of several processingcores, on-chip memory modules, and ThruChip Interface (TCI). We evaluate thescalability of SNACC with detailed simulation varying the number of cores andoff-chip memory access bandwidth. The results show that the energy efficiency of the accelerator becomes the highest in eight cores configuration with500MB/s off-chip bandwidth.

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A power management framework with simple DSL for automatic power-performance optimization on power-constrained HPC systems

Wada Y., He Y., Cao T., Kondo M.

ISSN 9783319699523

To design exascale HPC systems, power limitation is one of the most crucial and unavoidable issues; and it is also necessary to optimize the power-performance of user applications while keeping the power consumption of the HPC system below a given power budget. For this kind of power-performance optimization for HPC applications, it is indispensable to have enough information and good understanding about both the system specifications (what kind of hardware resources are included in the system, which component can be used as a “power-knob”, how to control the power-knob, etc.) and user applications (which part of the application is CPU-intensive, memory-intensive, and so on). Because this situation forces both the users and administrators of power-constrained HPC systems pay much effort and cost, it has been highly demanded to realize a simple framework to automate a power-performance optimization process, and to provide a simple user interface to the framework. To tackle these concerns, we propose and implement a versatile framework to help carry out power management and performance optimization on power-constrained HPC systems. In this framework, we also propose a simple DSL as an interface to utilize the framework. We believe this is a key to effectively utilize HPC systems under the limited power budget.

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